PLD, SPLD, GAL, CPLD, FPGA Design

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Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.
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Port is not connected when using top module
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Surah al Waqaih
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How to instantiate another vhd file inside testbench, where the testbench is used for opening files
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Surah al Waqaih
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[SOLVED] VHDL code "skip" a line in write procedure
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Surah al Waqaih
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VHDL Testbench (Weird output in the simulation)
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18
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Xenon02
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How to solve this issue of "No Hardware" in Quartus 13
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10
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FvM
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[SOLVED] Lattice FPGA: issue solved after re-flashing the same binary
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flote21
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Actel a1020b
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3
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772
FvM
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Direct connection of FPGA (spartan-6) to HDMI connector
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3
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856
D.A.(Tony)Stewart
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Aliexpress FPGAs are reliable?
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ThisIsNotSam
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how to set global include in synplify, like vivado "set global include"
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5
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FvM
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PLL implementation through FPGA
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6
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sushl
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SDRAM on CycloneV
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3
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ellahenderson2410
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Development FPGA board with Gowin chip
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5
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KlausST
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Memory (DDR) for image processing FPGA board application
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aminpix
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Watchdog timers and FPGA designs
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3
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1K
FvM
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Launch Simulation Error in Vivado
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1
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1K
dpaul
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FPGA timing, signaling between processes
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6
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1K
gahelton
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DE10-Standard reading states of switches by HPS
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732
Bruno812
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VHDL abs() function speed
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4
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gahelton
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How do I interpret "if" statement in different always_comb situations ?
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