Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

VHDL Testbench (Weird output in the simulation)

Xenon02

Full Member level 3
Joined
Nov 12, 2022
Messages
157
Helped
0
Reputation
0
Reaction score
0
Trophy points
16
Activity points
2,205
Hello !

Here is a problem in which I have been trying to fight with. The board is Basys3, the program is Vivado 2023.

1705869054789.png


it's not about those orange output from LEDs, I know why they work like that I guess.
But rather this outputs, they don't have any value ...

Here is the code for TOP :

Code:
entity TOP is
    Port ( btnR : in STD_LOGIC; -- Zmiana trybu świecenia
           btnC : in STD_LOGIC; -- włącz/wyłącz
           btnL : in STD_LOGIC; -- Zmiana prędkości świecenia 
           clk : in STD_LOGIC;
           led : out STD_LOGIC_VECTOR (7 downto 0));
end TOP;

architecture Behavioral of TOP is

signal COUT : STD_LOGIC := '0';
signal BTNR_O : STD_LOGIC := '0';
signal BTNC_O : STD_LOGIC := '0';
signal BTNL_O : STD_LOGIC := '0';
signal LED_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal LED_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";

begin

Debouncer: entity work.Debouncer PORT MAP (
        CLOCK_IN => clk,
        BIN => btnR,
        BOUT => BTNR_O
        );
Debouncer_1: entity work.Debouncer PORT MAP (
        CLOCK_IN => clk,
        BIN => btnC,
        BOUT => BTNC_O
        );  
Debouncer_2: entity work.Debouncer PORT MAP (
        CLOCK_IN => clk,
        BIN => btnL,
        BOUT => BTNL_O
        );      


end Behavioral;

Here is for the debouncer


Code:
entity Debouncer is
    port(   CLOCK_IN : in std_logic;
            BIN : in std_logic;
            BOUT : out std_logic
        );
end Debouncer;

architecture Behavioral of Debouncer is

--the below constants decide the working parameters.
--the higher this is, the more longer time the user has to press the button.
constant COUNT_MAX : integer := 2;
--set it '1' if the button creates a high pulse when its pressed, otherwise '0'.
constant BTN_ACTIVE : std_logic := '1';

signal count : integer := 0;
type state_type is (idle,wait_time); --state machine
signal state : state_type := idle;

begin
 
process(CLOCK_IN)
begin
    if(rising_edge(CLOCK_IN)) then
        case (state) is
            when idle =>
                if(BIN = BTN_ACTIVE) then 
                    state <= wait_time;
                else
                    state <= idle; --wait until button is pressed.
                end if;
                BOUT <= '0';
            when wait_time =>
                if(count = COUNT_MAX) then
                    count <= 0;
                    if(BIN = BTN_ACTIVE) then
                        BOUT <= '1';
                    end if;
                    state <= idle; 
                else
                    count <= count + 1;
                end if;
        end case;       
    end if;       
end process;           

end Behavioral;

And the testbench :


Code:
entity TOP_tb is
--  Port ( );
end TOP_tb;

architecture Behavioral of TOP_tb is

signal clk : std_logic := '0'; 
signal btnR : std_logic := '0'; -- Zmiana trybu świecenia
signal btnC : std_logic := '0'; -- włącz/wyłącz
signal btnL : std_logic := '0'; -- Zmiana prędkości świecenia
signal led : STD_LOGIC_VECTOR (7 downto 0) := "00000000";

begin

top_test: entity work.TOP PORT MAP (
      btnR => btnR,
      btnC => btnC,
      btnL => btnL,
      clk => clk,
      led => led
    );

CLOCK_IN_process :process
   begin
        clk <= '0';
        wait for 2ns;
        clk <= '1';
        wait for 2ns;
   end process;
  
Predkosc: process is -- Zmiana prędkości świecenia
    begin
        wait for 30ns;
        btnL <= '1'; wait for 24ns;
        btnL <= '0'; wait;
    end process;

Off_On: process is -- włącz/wyłącz
    begin
        btnC <= '1'; wait for 24ns;
        btnC <= '0'; wait;
    end process;
    
Mode: process is -- Proces zmiany trybu
    begin
        btnR <= '0'; wait;
    end process;

end Behavioral;
 
I don't understand what the red encircled signals are and how you added them to the waveform display. There are three debouncer instances in the design, entity signals can be only monitored per instance.
 
I don't understand what the red encircled signals are and how you added them to the waveform display. There are three debouncer instances in the design, entity signals can be only monitored per instance.

So I can't see the output ?
I mean I've added them just grabbing the entity :

1705871814115.png


Hmmm + something weird is happening.
Here is the schematic for the RTL

1705871894876.png


But for the Synthesis it adds new output to prescaller which is unconnected ... and many more weird thing ... I don't know where to find the error ...

1705872014725.png


This Prescallar and Debouncer are very weird ... like this FSM onehot count ... or mode2 takes a leds registor ? and in RTL it didn't ... I am so mixed up ...
 
Don't know how Vivado simulator shows hierarchical signals in waveform window. In my debugger, the signals would be shown with instance name.

The RTL schematic is for different code, there's no counter entity in the posted (probably incomplete) code.

Don't want to guess about inconsistent code.
 
Don't know how Vivado simulator shows hierarchical signals in waveform window. In my debugger, the signals would be shown with instance name.

The RTL schematic is for different code, there's no counter entity in the posted (probably incomplete) code.

Don't want to guess about inconsistent code.

Here are the rest :


Code:
entity Counter is
 Port (
        INPUT_C : in  STD_LOGIC; --Tutaj podajemy wyjście z przycisku odpowiadający za włączenie i wyłączenie
        INPUT_R : in  STD_LOGIC; --Tutaj podajemy wyjście z przycisku odpowiadający za zmianę trybu świecenia
        INPUT_1 : in  STD_LOGIC_VECTOR (7 downto 0); --wyjścia modu nr1 do tego wejścia
        INPUT_2 : in  STD_LOGIC_VECTOR (7 downto 0); --wyjścia modu nr2 do tego wejścia
        CLOCK_IN : in  STD_LOGIC;
        OUTPUT : out  STD_LOGIC_VECTOR (7 downto 0) --wyjście podłaczone do ledow
        );
end Counter;

architecture Behavioral of Counter is

signal count_r : integer := 0;
signal count_c : integer := 0;
signal output_multi : STD_LOGIC_VECTOR (7 downto 0):= "00000000"; --powiedzmy że output multiplexera
signal led_output : STD_LOGIC_VECTOR (7 downto 0):= "00000000"; --powiedzmy że output multiplexera
signal led_off : STD_LOGIC_VECTOR (7 downto 0):= "00000000"; -- ten wektor nie będzie zmieniany i ma służyć jako wyłączenie ledów

begin

OUTPUT <= led_output;

Counter : process (CLOCK_IN)
begin
    if(rising_edge(CLOCK_IN)) then
        if(INPUT_R = '1') then
            if(count_r = 0) then
                count_r <= 1;
                output_multi <= INPUT_1;
            else
                count_r <= 0;
                output_multi <= INPUT_2;
            end if;
        end if;
        if(INPUT_C = '1') then
            if(count_c = 0) then
                count_c <= 1;
                led_output <= output_multi;
            else
                count_c <= 0;
                led_output <= led_off;
            end if;
        end if;
    end if;
end process;
end Behavioral;

Code:
entity Mode7 is
 Port ( CLOCK_IN : in  STD_LOGIC;
        RESET : in  STD_LOGIC;
        TICK : in  STD_LOGIC;
        ledy_1 : out STD_LOGIC_VECTOR (7 downto 0)
        );
end Mode7;

architecture Behavioral of Mode7 is

signal count : natural := 0;
signal toggle : bit := '1';
signal leds : STD_LOGIC_VECTOR (7 downto 0):= "00000000";   


begin

ledy_1 <= leds;

Mode7_proc: process(CLOCK_IN, RESET) is
    begin
        if(RESET = '0') then
        count <= 0;
        toggle <= '1';
        leds <= "00000000";
        elsif(rising_edge(CLOCK_IN) and TICK = '1') then

                if(count <= 7) then
                    if(toggle = '1') then
                        leds(count) <= '1';
                        count <= count + 1;
                        if(count = 7) then
                            toggle <= not toggle;
                            count <= 7;
                        end if;
                    else
                        leds(count) <= '0';
                        count <= count - 1;
                        if(count = 0) then
                            toggle <= not toggle;
                            count <= 0;
                        end if;
                    end if;
                end if;
        end if;
end process;

end Behavioral;


Code:
entity Mode2 is
 Port ( CLOCK_IN : in  STD_LOGIC;
        RESET : in  STD_LOGIC;
        TICK : in  STD_LOGIC;
        ledy_2 : out STD_LOGIC_VECTOR (7 downto 0)
        );
end Mode2;

architecture Behavioral of Mode2 is

signal toggle : bit := '1';
signal leds : STD_LOGIC_VECTOR (7 downto 0):= "00000000";

begin

ledy_2 <= leds;

Mode2_proc: process(CLOCK_IN, RESET) is
    begin
           if(RESET = '0') then
              toggle <= '1';
              leds <= "00000000";
        elsif(rising_edge(CLOCK_IN) and TICK = '1') then
            if(toggle = '1') then
                leds <="10101010";
                toggle <= '0';
            else
                leds <="01010101";
                toggle <= '1';
            end if;
        end if;
end process;                               

end Behavioral;

Code:
entity Prescaler is
     Generic (
        prescalar : natural
     );
    Port ( INPUT : in STD_LOGIC;
           CLOCK_IN : in  STD_LOGIC;
           CLOCK_OUT : out  STD_LOGIC);
end Prescaler;

architecture Behavioral of Prescaler is
        signal count : natural := 0;
        signal count_speed : natural := 0;
        signal speed : natural := 2;
        signal INTER_CLOCK : STD_LOGIC := '0';
begin
    CLOCK_OUT <= INTER_CLOCK;

    Prescaler_proc: process(CLOCK_IN) is
    begin
        if(rising_edge(CLOCK_IN)) then
        
        if(INPUT = '1') then
            if(count_speed = 0) then
                count <= speed; -- prdko 0.5s
                count_speed <= 1;
            else
                count <= 0; -- prdko 1s
                count_speed <= 0;
            end if;
        else
            if(count >= prescalar - 1) then
                count <= 0;
                INTER_CLOCK <= '1';
            else
               INTER_CLOCK <= '0';
                count <= count + 1;
            end if;
        end if;
        
        end if;
    end process;

end Behavioral;


There is counter, mode2 and mode 7 and prescalar.
 
But no top level fitting the RTL schematic. Why not post a .zip file with consistent design files?
Oh I didn't know I can put in zip files here :D

Here it is, I just got lost, very lost ;D
--- Updated ---

@FvW what do you think about it ?
 

Attachments

  • Prure_edit.zip
    2.8 MB · Views: 50
Last edited:
The testbench has errors (multiple instances with same name, missing generic value), but all errors are for superfluous entities. tb should only instantiate top entity.

After deleting extra entities, top_tb compiles correctly and gives this output

1705910754551.png


This is the RTL schematic generated by Intel Quartus for the design

1705911151782.png
 
Yes the RTL looks ok but on synthesiz it does a lot of weird things and the simulation doesn't work well. Because the LEDs did not turn on, on the simulation. Can you send me the zip how did you modified the Testbench ? I would love to use it to find errors in my code. Btw btnC rolę is to turn on or off the device
 
I presume the design is working as coded. I don't know what your requirements are, if it's behaving other than expected, it's probably coded incorrectly.
 

Attachments

  • TOP_tb.zip
    854 bytes · Views: 49
I presume the design is working as coded. I don't know what your requirements are, if it's behaving other than expected, it's probably coded incorrectly.

Probably yes but trying to find why.
Basically there are 3 buttons and 2 LEDs Mode (the way they light blink like every second led to light up each second etc.). If I click btnC middle button then it turns on or off the LEDs. If I click right button btnR then it changes the mode from mode7 to mode 2 and from mode 2 to mode 7 if I click again.
The left button btnL is for the speed of LEDs to blink. From 1 s to 0.5s and from 0.5 to 1 if I click again

The counter is there to count how many times I have clicked the button and pick which mode to choose like multiplexer.
The debouncer is I guess known.
Prescallar is to change 100MHz into 1 Hz.

Yea and the LEDs do not work and it does weird synthesiz schematic ...
 
I presume the design is working as coded. I don't know what your requirements are, if it's behaving other than expected, it's probably coded incorrectly.
I've used the testbench you've sent to me and it still has empty space when checking like debouncer

1705943368724.png

EDIT:

After some checkout, I think the Counter entity might be the problem but I can't find the error in the code.
Because In the simulation the Counter works the way that he sees the inputs I guess he increments the counter integer (can't see if it does in the simulation don't know how to put it on), but the output always stays "0",

Code:
entity Counter is
 Port (
        INPUT_C : in  STD_LOGIC; --Tutaj podajemy wyjście z przycisku odpowiadający za włączenie i wyłączenie
        INPUT_R : in  STD_LOGIC; --Tutaj podajemy wyjście z przycisku odpowiadający za zmianę trybu świecenia
        INPUT_1 : in  STD_LOGIC_VECTOR (7 downto 0); --wyjścia modu nr1 do tego wejścia
        INPUT_2 : in  STD_LOGIC_VECTOR (7 downto 0); --wyjścia modu nr2 do tego wejścia
        CLOCK_IN : in  STD_LOGIC;
        OUTPUT : out  STD_LOGIC_VECTOR (7 downto 0) --wyjście podłaczone do ledow
        );
end Counter;

architecture Behavioral of Counter is

signal count_r : integer := 0;
signal count_c : integer := 0;
signal output_multi : STD_LOGIC_VECTOR (7 downto 0); --powiedzmy że output multiplexera
signal led_output : STD_LOGIC_VECTOR (7 downto 0):= "00000000"; --powiedzmy że output multiplexera
signal led_off : STD_LOGIC_VECTOR (7 downto 0):= "00000000"; -- ten wektor nie będzie zmieniany i ma służyć jako wyłączenie ledów

begin

Counter : process (CLOCK_IN)
begin
    if(rising_edge(CLOCK_IN)) then
        if(rising_edge(INPUT_R)) then
            if(count_r = 0) then
                count_r <= 1;
                output_multi <= INPUT_1;
            else
                count_r <= 0;
                output_multi <= INPUT_2;
            end if;
        end if;
        if(rising_edge(INPUT_C)) then
            if(count_c = 0) then
                count_c <= 1;
                led_output <= output_multi;
            else
                count_c <= 0;
                led_output <= led_off;
            end if;
        end if;
    end if;
end process;

OUTPUT <= led_output;
end Behavioral;

I which he sees that INPUT_C is rising (I also testes for INPUT_C = '1' didn't work), but it still doesn't get the output work.

1705946959040.png


Can I connect two internal signals with each other ?
 
Last edited:
In the counter process, are you expecting the rising_edges of CLOCK_IN and INPUT_R to be synchronous? Same for rising edges for CLOCK_IN and INPUT_C. The logic is not going to be able to meet up with these conditions. Don't check for rising edges of INPUT_C and INPUT_R.
--- Updated ---

If you must check for rising edges of INPUT_C and INPUT_R, then disregard CLOCK_IN.
 
In the counter process, are you expecting the rising_edges of CLOCK_IN and INPUT_R to be synchronous? Same for rising edges for CLOCK_IN and INPUT_C. The logic is not going to be able to meet up with these conditions. Don't check for rising edges of INPUT_C and INPUT_R.
--- Updated ---

If you must check for rising edges of INPUT_C and INPUT_R, then disregard CLOCK_IN.

Yup found the result.
It wasn't the rising edges but rather the code itself.

I've decided to update the output a bit differently. Here is the code for the counter :



Code:
entity Counter is
 Port (
        INPUT_C : in  STD_LOGIC;
        INPUT_R : in  STD_LOGIC;
        INPUT_1 : in  STD_LOGIC_VECTOR (7 downto 0);
        INPUT_2 : in  STD_LOGIC_VECTOR (7 downto 0);
        CLOCK_IN : in  STD_LOGIC;
        OUTPUT : out  STD_LOGIC_VECTOR (7 downto 0)
        );
end Counter;

architecture Behavioral of Counter is

signal count_r : integer := 0;
signal count_c : integer := 0;
signal output_multi : STD_LOGIC_VECTOR (7 downto 0):= "00000000";
signal led_output : STD_LOGIC_VECTOR (7 downto 0):= "00000000";
signal led_off : STD_LOGIC_VECTOR (7 downto 0):= "00000000";

-- Dodajemy sygnały do przechowywania poprzednich stanów INPUT_R i INPUT_C
signal prev_INPUT_R : STD_LOGIC := '0';
signal prev_INPUT_C : STD_LOGIC := '0';

begin

Counter : process (CLOCK_IN)
begin
    if(rising_edge(CLOCK_IN)) then
        -- Zamiast rising_edge(INPUT_R), sprawdzamy, czy INPUT_R zmienił się z '0' na '1'
        if(INPUT_R = '1' and prev_INPUT_R = '0') then
            if(count_r = 0) then
                count_r <= 1;
            else
                count_r <= 0;
            end if;
        end if;
        -- Zamiast rising_edge(INPUT_C), sprawdzamy, czy INPUT_C zmienił się z '0' na '1'
        if(INPUT_C = '1' and prev_INPUT_C = '0') then
            if(count_c = 0) then
                count_c <= 1;
            else
                count_c <= 0;
            end if;
        end if;
        -- Aktualizujemy poprzednie stany INPUT_R i INPUT_C
        
        if(count_r = 0) then
            output_multi <= INPUT_2;
        else
            output_multi <= INPUT_1;
        end if;
        
        if(count_c = 0) then
            led_output <= led_off;
        else
            led_output <= output_multi;
        end if;
        
        prev_INPUT_R <= INPUT_R;
        prev_INPUT_C <= INPUT_C;
    end if;
end process;

OUTPUT <= led_output;
end Behavioral;

The output has a delay about 2 cycles but it's okey for now, it works.
 
Really!?
Put back the rising_edge keyword for INPUT_C and INPUT_R let's see how your updated code will behave.

Yea I've added the rising_edge it didn't work yea, but basically even in the old code if I deleted the rising_edge it still had this problem, but changing the code like above it worked.
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top