[SOLVED] VHDL code "skip" a line in write procedure

[Raeiu]

Hi everyone, first of all sorry for my bad english.
I have a problem with this code. It generates a csv file where writes stimuli for a TB (external).
It writes a first line of text with signals name, in the second line should write the first test case (text), after this writes signals and then: second test case, signals, third test case ecc.

An example of what i would like to achieve:

#simENA	D	Reset	Enable	CLK
#TC-1
0	0	1	0	1
1	0	1	0	0
...	...	...	...	...
#TC-2
...	...	...	...	...
#TC-3
...	...	...	...	...

But it "skip" the second line of text: it writes a line of signals and after #TC-1 and i don't understand why. (see attach file)
For write test cases texts i used a process that, when the signal test_case is '1', signal tc_write write the line, test_case turn '0', wait for xx ns, and then the signals (surely there is a better way to do this).
I hope I was clear in my explanation.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
USE STD.ENV.STOP;

ENTITY write_stimuli IS
END write_stimuli;

ARCHITECTURE RTL OF write_stimuli IS

    SIGNAL simCLK     : STD_LOGIC;        --simulation clk
    SIGNAL simENA    : STD_LOGIC;        --simulation enable. It's used on tb (external)
    SIGNAL write_tc    : STRING(1 TO 32);
    SIGNAL test_case: STD_LOGIC;
   
--*************************************************************************************
-- FUNCTION STRING PAD
--*************************************************************************************
    FUNCTION PADDED_STRING(s: STRING; n: POSITIVE) RETURN STRING IS
        VARIABLE ps: STRING(1 TO n) := (OTHERS => ' ');
            BEGIN
            IF s'LENGTH >= n THEN
                ps := s(1 TO n); --- truncate string
            ELSE
                ps(1 TO s'LENGTH) := s;
                ps(s'LENGTH + 1 TO n) := (OTHERS => ' ');
            END IF;
        RETURN ps;
    END;

--*************************************************************************************
-- PROCEDURE
--*************************************************************************************
    PROCEDURE PWRITE(VARIABLE l: INOUT LINE; msg: IN STRING) IS
        VARIABLE tab : CHARACTER := ';';
        BEGIN
            WRITE(l, msg);
            WRITE(l, tab);
    END PROCEDURE;
   
    PROCEDURE PWRITE(VARIABLE l: INOUT LINE; sig: IN STD_LOGIC) IS
        VARIABLE tab : CHARACTER := ';';
        BEGIN
            WRITE(l, sig);
            WRITE(l, tab);
    END PROCEDURE;
   
    PROCEDURE TCWRITE(VARIABLE l: INOUT LINE; sig: IN STRING; FILE f: TEXT) IS
        VARIABLE tab : CHARACTER := ';';
        BEGIN
            WRITE(l, sig);
            WRITE(l, tab);
            WRITELINE(f, l);
    END PROCEDURE;
   

--*************************************************************************************
-- DICHIARAZIONE DEI SEGNALI
--
-- In questa sezione bisogna scrivere i segnali preceduti dal prefisso
-- "my". Questi sono i segnali necessari per la simulazione.
--*************************************************************************************
    SIGNAL reset : STD_LOGIC;
    SIGNAL enable : STD_LOGIC;
    SIGNAL clk    : STD_LOGIC;
    SIGNAL D        : STD_LOGIC;
    SIGNAL Q        : STD_LOGIC;
   
    BEGIN

    write_process: PROCESS
        FILE stimulus     : TEXT OPEN WRITE_MODE IS ("Stimoli.csv");
        VARIABLE lo     : LINE;
        VARIABLE tab     : CHARACTER := ';';
        VARIABLE text_done : BOOLEAN := FALSE;
        VARIABLE cont    : natural := 1;
            BEGIN
                IF (text_done = FALSE) THEN                    -- Write first line on csv
                    PWRITE(lo, "#simENA");
                    PWRITE(lo, "D");      
                    PWRITE(lo, "reset");
                    PWRITE(lo, "enable");
                    PWRITE(lo, "clk");
                    PWRITE(lo, "EXPECTED");
                    PWRITE(lo, "Q");
                    PWRITE(lo, "RESULT");
                    WRITELINE(stimulus, lo);
                    text_done := TRUE;
                END IF;
                   
                IF (text_done = TRUE) THEN                     -- write test case
                    IF (test_case = '1') THEN
                        TCWRITE(lo, write_tc, stimulus);
                    END IF;
                END IF;
               
                IF (text_done = TRUE) THEN                    -- Write signals on csv
                    WAIT UNTIL simCLK <= '1';                  
                    PWRITE(lo, simENA);
                    PWRITE(lo, D);      
                    PWRITE(lo, reset);
                    PWRITE(lo, enable);
                    PWRITE(lo, clk);
                    PWRITE(lo, string'(" "));
                    PWRITE(lo, Q);
                    PWRITE(lo, string'(" "));
                    WRITELINE(stimulus, lo);
                    cont := cont + 1;
                        IF (cont = 30) THEN
                            FILE_CLOSE(stimulus);
                            STOP;
                        END IF;
                END IF;
    END PROCESS;
--*************************************************************************************
-- SIGNAL PROCESS
--*************************************************************************************
        simENA_process: PROCESS
        BEGIN
            simENA <= '0';
            WAIT FOR 10 ns;
            simENA <= '1';
            WAIT FOR 70 ns;
            simENA <= '0';
            WAIT FOR 10 ns;
            simENA <= '1';
            WAIT;
    END PROCESS;
   
   
    D_process: PROCESS
        BEGIN  
            D <= '0';
            WAIT FOR 40 ns;
            D <= '1';
            WAIT FOR 80 ns;
            D <= '0';
            WAIT FOR 20 ns;
            D <= '1';
            WAIT;
    END PROCESS;
           
       
    reset_PROCESS: PROCESS
        BEGIN
            reset <= '1';
            WAIT FOR 10 ns;
            reset <= '0';
            WAIT FOR 30 ns;
            reset <= '1';
            WAIT FOR 10 ns;
            reset <= '0';
            WAIT FOR 30 ns;
            reset <= '1';
            WAIT;
    END PROCESS;
           

    enable_process: PROCESS
        BEGIN
            enable <= '0';
            WAIT FOR 80 ns;
            enable <= '1';
            WAIT FOR 80 ns;
            enable <= '0';
            WAIT FOR 30 ns;
            enable <= '1';
            WAIT;
    END PROCESS;
           
   
    myclk_process: PROCESS
        BEGIN
            clk <= '0';
            WAIT FOR 10 ns;
            clk <= '1';
            WAIT FOR 10 ns;
    END PROCESS;
           
           
    Q_process: PROCESS
        BEGIN
            Q <= '0';
            WAIT FOR 20 ns;
            Q <= '1';
            WAIT FOR 20 ns;
            Q <= '0';
            WAIT FOR 20 ns;
            Q <= '1';
            WAIT FOR 20 ns;
            Q <= '0';
            WAIT;
    END PROCESS;
--*************************************************************************************
-- SIMULATION CLK
--*************************************************************************************
    simCLK_process: PROCESS
        BEGIN
        simCLK <= '0';
        WAIT FOR 10 ns;
        simCLK <= '1';
        WAIT FOR 10 ns;
    END PROCESS;
--*************************************************************************************
-- WRITE TEST CASE
--*************************************************************************************
write_TC_process: PROCESS
        BEGIN
            test_case <= '1';                                  
            write_tc <= PADDED_STRING("#TC-1", 32);
            WAIT FOR 10 ns;
            test_case <= '0';
            WAIT FOR 60 ns;
            test_case <= '1';
            write_tc <= PADDED_STRING("#TC-2", 32);
            WAIT FOR 10 ns;
            test_case <= '0';
            WAIT FOR 20 ns;
            test_case <= '1';
            write_tc <= PADDED_STRING("#TC-3", 32);
            WAIT FOR 10 ns;
            test_case <= '0';
            WAIT FOR 40 ns;
            test_case <= '1';
            write_tc <= PADDED_STRING("#TC-4", 32);
            WAIT FOR 10 ns;
            test_case <= '0';
            WAIT;
    END PROCESS;
   
END RTL;

 

[KlausST]

Hi,

I´m not a specialist in VHDL ..

but on a quick view it seems you expect the code to be processed line after line like in a processor.
But this isn´t the case with VHDL. The code is processed in parallel.

Thus I guess writing line#2 and line #3 follow the same condition, thus the latest true "condition" wins.

--> A solution can be to use a variable to count for lines.
Basically coding a state machine that switches state after the currently running function has finished

****

Example: (pseudo code)
* i = 1
* if I = 1 then do function A
* ...
* if I = 1 then do function B

Results in "doing function B" only. Function A never becomes processed.
The line " if I = 1 then do function A" is basically useless.

****

VHDL is hardware description. Thus learn to think "as parallel processing hardware" -- for get about "serial processing software".

Klaus

 

[Raeiu]

Sorry but i'm a little rusty with VHDL. I write a fsm with this logic:

1. if simRESET = '1', stay state 0 (st0) else next_state
2. if simRESET = '0' pass on st1
3. In st1 if test_done = false write first line text. If test_done = true pass on st2
4. in st2 if test_case = '1' write line of text TC else pass on st3
5. in st3 if test_case = '0' write signals else return on st2. If cont = 30 close file and stop

Simulation does nothing i must kill the run. Here the code:

fsm_process: PROCESS(simRESET)
        BEGIN
            if (simRESET = '1') THEN
                state <= st0;
            else
                state <= next_state;
            end if;
    END PROCESS;
    
    write_process: PROCESS
        FILE stimulus     : TEXT OPEN WRITE_MODE IS ("Stimoli.csv");
        VARIABLE lo     : LINE;
        VARIABLE tab     : CHARACTER := ';';
        VARIABLE text_done : BOOLEAN := FALSE;
        VARIABLE cont    : natural := 1;
            BEGIN
                case state IS
                    
                    when st0 =>
                        if(simRESET = '1')THEN
                            next_state <= st0;
                        ELSE
                            next_state <= st1;
                        end if;
                            
                    when st1 =>
                        if(text_done = FALSE)then
                            PWRITE(lo, "#simENA");
                            PWRITE(lo, "D");       
                            PWRITE(lo, "reset");
                            PWRITE(lo, "enable");
                            PWRITE(lo, "clk");
                            PWRITE(lo, "EXPECTED");
                            PWRITE(lo, "Q");
                            PWRITE(lo, "RESULT");
                            WRITELINE(stimulus, lo);
                            text_done := true;
                        end if;
                        
                        if (text_done = true) then
                            next_state <= st2;
                        end if;
                        
                    when st2 =>   
                        if (test_case = '1') then
                            TCWRITE(lo, write_tc, stimulus);
                        else
                            next_state <= st3;
                        end if;
                
                    when st3 =>
                        if (test_case = '0') THEN
                            WAIT UNTIL simCLK <= '1';                   
                            PWRITE(lo, simENA);
                            PWRITE(lo, D);       
                            PWRITE(lo, reset);
                            PWRITE(lo, enable);
                            PWRITE(lo, clk);
                            PWRITE(lo, string'(" "));
                            PWRITE(lo, Q);
                            PWRITE(lo, string'(" "));
                            WRITELINE(stimulus, lo);
                            cont := cont + 1;
                            IF (cont = 30) THEN
                                next_state <= st4;
                            END IF;
                        ELSE
                            next_state <= st2;
                        END if;
                        
                    when st4 =>
                        FILE_CLOSE(stimulus);
                        STOP;
                end case;
    END PROCESS;

Can someone help me please?

 

[KlausST]

Hi,

I'm taking about this:

    write_process: PROCESS
        FILE stimulus     : TEXT OPEN WRITE_MODE IS ("Stimoli.csv");
:
:
:                 
                IF (text_done = TRUE) THEN                     -- write test case
                    IF (test_case = '1') THEN
                        TCWRITE(lo, write_tc, stimulus);
                    END IF;
                END IF;
             
                IF (text_done = TRUE) THEN                    -- Write signals on csv
                    WAIT UNTIL simCLK <= '1';

(Sadly one can not give text a color in a CODE window)
Ther is twice: " IF (text_done = TRUE) THEN "

Both tasks are in the same process.
Both tasks will start at the same time, will try to work in parallel .... and may collide.

***
As said, I´m not a specialist. Maybe others can help you with coding.

Klaus

 

[Raeiu]

I understood what you meant. I'm waiting for someone who knows more about vhdl

 

[FvM]

Do you mind to post complete code of your test? Present code is missing some signal declarations.

 

[Raeiu]

Do you mind to post complete code of your test? Present code is missing some signal declarations.

Sure. I had truble whit my internet line.
(To compact i have attached the files).
i did some modification. Now the code doesn't crash but it still doesn't write.

P.S: text_write write first line on csv with signals names and tc_write write tests cases.

EDIT: i saw that the fsm has been written bad. Now the code write on csv: first line of text, first test case and signals (bad). I think there is a problem on a case c. It don't switch at status b when tc_write = '1'

 

[Raeiu]

Semi-solved. First the code:
FSM

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use std.env.stop;

entity fsm_stimuli is
    port(
   
    --    FSM SIGNALS
        signal FSMclk             : in std_logic;
        signal FSMtc_write         : in std_logic;
        signal FSMtext_write     : in std_logic;
        signal FSMwrite_tc         : in string(1 to 32);
       
    --    COMPONENT SIGNALS
        signal COMPsimena         : in std_logic;
        signal COMPpreset         : in std_logic;
        signal COMPreset         : in std_logic;
        signal COMPenable         : in std_logic;
        signal COMPclk            : in std_logic;
        signal COMPd             : in std_logic;
        signal COMPq             : in std_logic
    );
end fsm_stimuli;

architecture rtl of fsm_stimuli is
--*************************************************************************************
-- PROCEDURE
--*************************************************************************************
    procedure pwrite(variable l: inout line; msg: in string) is
        variable tab : character := ';';
        begin
            write(l, msg);
            write(l, tab);
    end procedure;
   
    procedure pwrite(variable l: inout line; sig: in std_logic) is
        variable tab : character := ';';
        begin
            write(l, sig);
            write(l, tab);
    end procedure;
   
    procedure ptcwrite(variable l: inout line; sig: in string; file f: text) is
        variable tab : character := ';';
        begin
            write(l, sig);
            write(l, tab);
            writeline(f, l);
    end procedure;
   
--********************************************************************************
--    STATE DECLARETION
--********************************************************************************
   
    type states is (write_sig_name, write_csv);
    signal state : states;
   
--********************************************************************************
-- WRITING PROCESS
--********************************************************************************
    begin
        process (FSMclk, FSMtc_write, FSMtext_write)
       
        file stimulus     : text open write_mode is ("stimoli.csv");
        variable lo     : line;
        variable tab     : character := ';';
        variable cont     : natural := 0;
               
            begin
                if (FSMtext_write = '1') then
                    state <= write_sig_name;
                else
                    case state is
                       
                        when write_sig_name =>                            -- write first line on csv with signals names
                            if (FSMclk = '1') then
                                pwrite(lo, "#simENA");
                                pwrite(lo, "D");      
                                pwrite(lo, "reset");
                                pwrite(lo, "preset");
                                pwrite(lo, "enable");
                                pwrite(lo, "clk");
                                pwrite(lo, "--EXPECTED--");
                                pwrite(lo, "Q");
                                pwrite(lo, "--RESULT--");
                                writeline(stimulus, lo);
                            end if;
                            if (FSMtext_write = '0') then
                                state <= write_csv;
                            end if;
                       
                        when write_csv =>
                       
                            if (FSMtc_write = '1') then                    -- write tests cases and signals on csv
                                ptcwrite(lo, FSMwrite_tc, stimulus);
                            elsif (FSMtc_write = '0') then
                                pwrite(lo, COMPsimena);
                                pwrite(lo, COMPd);      
                                pwrite(lo, COMPreset);
                                pwrite(lo, COMPpreset);
                                pwrite(lo, COMPenable);
                                pwrite(lo, COMPclk);
                                pwrite(lo, string'(" "));
                                pwrite(lo, COMPq);
                                pwrite(lo, string'(" "));
                                writeline(stimulus, lo);
                           
                                cont := cont + 1;
                                if (cont = 30) then                         -- counter for stop simulation and close file
                                    file_close(stimulus);
                                    stop;
                                end if;
                            end if;
                    end case;
                end if;
        end process;  
end rtl;

TB:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity write_stimuli_tb is
end write_stimuli_tb;

architecture rtl of write_stimuli_tb is
--*************************************************************************************
-- COMPONENT DECLARATION
--*************************************************************************************
    component fsm_stimuli is
        port(
       
    --    FSM SIGNALS
        signal FSMclk             : in std_logic;
        signal FSMtc_write         : in std_logic;
        signal FSMtext_write     : in std_logic;
        signal FSMwrite_tc         : in string(1 to 32);
       
    --    COMPONENT SIGNALS
        signal COMPsimena     : in std_logic;
        signal COMPpreset     : in std_logic;
        signal COMPreset     : in std_logic;
        signal COMPenable     : in std_logic;
        signal COMPclk        : in std_logic;
        signal COMPd         : in std_logic;
        signal COMPq         : in std_logic
        );
    end component;
   
--*************************************************************************************
-- SIGNALS DECLARATION
--*************************************************************************************
    -- SIGNALS FOR FSM
    signal FSMclk              : std_logic;
    signal FSMtc_write         : std_logic;
    signal FSMtext_write     : std_logic;
    signal FSMwrite_tc         : string(1 to 32);
   
    -- SIGNALS FOR COMPONENT
    signal COMPsimena     : std_logic;
    signal COMPpreset     : std_logic;
    signal COMPreset     : std_logic;
    signal COMPenable     : std_logic;
    signal COMPclk        : std_logic;
    signal COMPd         : std_logic;
    signal COMPq         : std_logic;
   

   
--*************************************************************************************
-- STRING PAD FUNCTION
--*************************************************************************************
    function padded_string(s: string; n: positive) return string is
        variable ps: string(1 to n) := (others => ' ');
            begin
            if s'length >= n then
                ps := s(1 to n); --- tronca la stringa
            else
                ps(1 to s'length) := s;
                ps(s'length + 1 to n) := (others => ' ');
            end if;
        return ps;
    end;

   
    begin
--*************************************************************************************
-- UUT DECLARATION
--*************************************************************************************
        uut: fsm_stimuli port map(
            FSMclk => FSMclk,
            FSMtc_write => FSMtc_write,
            FSMtext_write => FSMtext_write,
            FSMwrite_tc => FSMwrite_tc,
            COMPsimena => COMPsimena,
            COMPpreset => COMPpreset,
            COMPreset => COMPreset,
            COMPenable => COMPenable,
            COMPclk => COMPclk,
            COMPd => COMPd,
            COMPq => COMPq
            );
--*************************************************************************************
-- SIGNALS PROCESS
--*************************************************************************************
        simena_process: process
        begin
            COMPsimena <= 'Z';
            wait for 20 ns;
            COMPsimena <= '0';
            wait for 10 ns;
            COMPsimena <= '1';
            wait for 70 ns;
            COMPsimena <= '0';
            wait for 10 ns;
            COMPsimena <= '1';
            wait;
    end process;
   
   
    d_process: process
        begin
            COMPd <= 'Z';
            wait for 20 ns;
            COMPd <= '0';
            wait for 40 ns;
            COMPd <= '1';
            wait for 80 ns;
            COMPd <= '0';
            wait for 20 ns;
            COMPd <= '1';
            wait for 20 ns;
            COMPd <= '0';
            wait;
    end process;
           
       
    myreset_process: process
        begin
            COMPreset <= 'Z';
            wait for 20 ns;
            COMPreset <= '1';
            wait for 10 ns;
            COMPreset <= '0';
            wait for 30 ns;
            COMPreset <= '1';
            wait for 10 ns;
            COMPreset <= '0';
            wait for 30 ns;
            COMPreset <= '1';
            wait for 20 ns;
            COMPreset <= '0';
            wait for 100 ns;
            COMPreset <= '1';
            wait for 10 ns;
            COMPreset <= '0';
            wait for 10 ns;
            COMPreset <= '1';
            wait;
    end process;
           

    mypreset_process: process
        begin
            COMPpreset <= 'Z';
            wait for 20 ns;
            COMPpreset <= '0';
            wait for 20 ns;
            COMPpreset <= '1';
            wait for 10 ns;
            COMPpreset <= '0';
            wait for 30 ns;
            COMPpreset <= '1';
            wait for 10 ns;
            COMPpreset <= '0';
            wait for 140 ns;
            COMPpreset <='1';
            wait;
    end process;
           

    myenable_process: process
        begin
            COMPenable <= 'Z';
            wait for 20 ns;
            COMPenable <= '0';
            wait for 80 ns;
            COMPenable <= '1';
            wait for 80 ns;
            COMPenable <= '0';
            wait for 30 ns;
            COMPenable <= '1';
            wait;
    end process;
           
   
    myclk_process: process
        begin
            COMPclk <= '0';
            wait for 10 ns;
            COMPclk <= '1';
            wait for 10 ns;
    end process;
           
           
    myq_process: process
        begin
            COMPq <= 'Z';
            wait for 20 ns;
            COMPq <= '0';
            wait for 20 ns;
            COMPq <= '1';
            wait for 20 ns;
            COMPq <= '0';
            wait for 20 ns;
            COMPq <= '1';
            wait for 20 ns;
            COMPq <= '0';
            wait for 30 ns;
            COMPq <= '1';
            wait for 20 ns;
            COMPq <= '0';
            wait for 20 ns;
            COMPq <= '1';
            wait for 50 ns;
            COMPq <= '0';
            wait for 10 ns;
            COMPq <= '1';
            wait for 10 ns;
            COMPq <= '0';
            wait;
    end process;
--*************************************************************************************
-- FSM CLOCK
--*************************************************************************************
    simclk_process: process
        begin
        FSMclk <= '1';
        wait for 10 ns;
        FSMclk <= '0';
        wait for 10 ns;
    end process;
--*************************************************************************************
-- FSM TEXT WRITE
--*************************************************************************************
    simtext_write_process: process
        begin
            FSMtext_write <= '1';
            wait for 5 ns;
            FSMtext_write <= '0';
            wait;
    end process;
--*************************************************************************************
-- FSM TESTS CASES WRITE
--*************************************************************************************
write_tc_process: process
        begin
            FSMtc_write <= '0';
            wait for 10 ns;
            FSMtc_write <= '1';
            FSMwrite_tc <= padded_string("#tc-1", 32);                                  
            wait for 10 ns;
            FSMtc_write <= '0';
            wait for 60 ns;
            FSMtc_write <= '1';
            FSMwrite_tc <= padded_string("#tc-2", 32);
            wait for 10 ns;
            FSMtc_write <= '0';
            wait for 20 ns;
            FSMtc_write <= '1';
            FSMwrite_tc <= padded_string("#tc-3", 32);
            wait for 10 ns;
            FSMtc_write <= '0';
            wait for 40 ns;
            FSMtc_write <= '1';
            FSMwrite_tc <= padded_string("#tc-4", 32);
            wait for 10 ns;
            FSMtc_write <= '0';
            wait;
    end process;
   
end rtl;

The problem is here:

if (FSMtc_write = '1') then                    -- write tests cases and signals on csv

                                ptcwrite(lo, FSMwrite_tc, stimulus);

                            elsif (FSMtc_write = '0') then

                                pwrite(lo, COMPsimena);

                                pwrite(lo, COMPd);
                                ....
                                ....
                                ....

When FSMtc_write = '1' it write test case and it work but doesn't write signal at the same step (see attached file). The signals highlighted in red are not written.

I thought to add anoter state after write_csv i tried something like this:

.....
when write_csv =>
    if (FSMtc_write = '1') then                    -- write tests cases and signals on csv
    ptcwrite(lo, FSMwrite_tc, stimulus);
    else
        write_sig <= '1';            -- signal declared to write signals on csv
        state <= write_signals
    end if;
   
when write_signals =>
    --pwrite all signals
    cont := cont + 1;
if (cont = 30) then                         -- counter for stop simulation and close file
          file_close(stimulus);
          stop;
end if;

    if (tc_write = '1') then
        write_sig <= '0';
        state <= write_csv;
    end if;

write_sig is declared in architecture of fsm. it's a flag for write signals on csv. But this code doesn't work: the simulation doesn't stop and csv is written badly.

Any suggestion?

EDIT: Solved in this way: added pwrite(signal) in statement FSMtc_write = '1' in write_csv state.

 

[Surah al Waqaih]

Code looks good! To tackle the skipped line issue, double-check the timing of test_case transitions. Simplifying the test case handling might enhance clarity. Happy coding