Memory (DDR) for image processing FPGA board application

[aminpix]

I am in the process of designing an image processing board with a Xilinx FPGA on it (possibly Kintex or Zynq).
This board has Two cameras, a HDMI-in and a HDMI-out interfaces.
I am not very professional in image processing, but I assume the developers will need lots of DDR memory, especially because it has HDMI in and out interface.
Also, I know we need some RAM for microblaze (or PS part in Zynq) to boot linux on the FPGA.
My questions are:

1- Should we have two sets of DDR memories on the FPGA (one for PS and one set for PL section)? I mean one SODIMM ram for PL part and one fly-by topology for PS section.
2- What is your recommended memory sizes for this board? I am thinking about a 1Gb DDR4 for PS (or Microblaze) part and a SODIMM for PL part.

Cheers

 

[dpaul]

Q> Do you want to store the data inside the DDR* before processing or after its processing?

Generally speaking, the size of the large buffer (here DDR3) memory depends on how fast data is being moved in (continuous data or intermittent) and how fast it is being read out from the DDR*. If the read out from the DDR* is slow (for whatever reason) but the logic before the DDR* pushes in data really fast, then you need a large sized memory. While if the read out from DDR* is fast, but your data pipeline is slow after the images/video moves in to the FPGA, then a smaller sized DDR* memory will suffice. Such things you need to consider.

 

[aminpix]

The HDMI data rates is 6Gbps and I assume a few frames are needed to be processed at time. (I am not sure about the image processing algorithm, but I guess Should be this way). Therefore DDR must be enough size to buffer in, buffer out and process few frames at time.

How about the PS memory?
Should I separate it from PL memory?

Q> Do you want to store the data inside the DDR* before processing or after its processing?

Generally speaking, the size of the large buffer (here DDR3) memory depends on how fast data is being moved in (continuous data or intermittent) and how fast it is being read out from the DDR*. If the read out from the DDR* is slow (for whatever reason) but the logic before the DDR* pushes in data really fast, then you need a large sized memory. While if the read out from DDR* is fast, but your data pipeline is slow after the images/video moves in to the FPGA, then a smaller sized DDR* memory will suffice. Such things you need to consider.

y?

 

[KlausST]

Hi,

I assume a few frames are needed to be processed at time. (I am not sure about the image processing algorithm

If you don´t know, who knows? We can´t know.
Image processing could be from very basic brightness control .. to feedbacked brightness regulation .. to 3D pattern recognition ...

So imagine this situation:
You are a painter. ...
And a customer asks for a quote. But states he does not know how many rooms, the wall sizes, what color type.

This describes about our situation: We like to help (the painter wants to give a quote) but we are not able to do so.

We don´t know pixel count of the picture, we don´t know color depth, we don´t know what algorithm is used and how many frames need to be involved.

**
So we can recommend: use two (or more) interfaces, use more RAM than you expect now, design eveything bigger than expected, just not to run low on ressources.

Or you could run a very realistic simulation - which (i guess) is a lot of effort.

Or save money and use only minimal hardware .. and risk you need to do a redesign ... or two...

It´s really hard to recommend the right strategy.


Klaus

 

[aminpix]

Since the FPGA team is not started their job yet, I have to use a SODIMM memory for PL part for flexibility.
I wonder how about PS or Linux part?
Should I have separate Fly-by DDR topology for PS memory? Or can I use 1G of the SODIMM memory for Linux (PS)?

 

[dpaul]

Then please ask someone in the FPGA team who is responsible for the architecture. That person should be able to tell you (if he/she has done some basic calculations) how much memory is needed needed for the PL part.

 

[FlyingDutch]

I am in the process of designing an image processing board with a Xilinx FPGA on it (possibly Kintex or Zynq).
This board has Two cameras, a HDMI-in and a HDMI-out interfaces.
I am not very professional in image processing, but I assume the developers will need lots of DDR memory, especially because it has HDMI in and out interface.
Also, I know we need some RAM for microblaze (or PS part in Zynq) to boot linux on the FPGA.
My questions are:

1- Should we have two sets of DDR memories on the FPGA (one for PS and one set for PL section)? I mean one SODIMM ram for PL part and one fly-by topology for PS section.
2- What is your recommended memory sizes for this board? I am thinking about a 1Gb DDR4 for PS (or Microblaze) part and a SODIMM for PL part.

Cheers

Hello,
it is easier (PCB design) to use external SPI PSRAM or HyperRAM ICs.

Best Regards

 

[KlausST]

Hi,

I doubt you can do real time video processing using SPI connected RAM.

Klaus

 

[dpaul]

Hello,
it is easier (PCB design) to use external SPI PSRAM or HyperRAM ICs.

Best Regards

Unfortunately that is not the answer what the OP is looking for; this thread is not regarding the nature of external memory! He wants to calc or find out a way to calc the max amount of DDR* memory needed for his application.

 

[aminpix]

Unfortunately that is not the answer what the OP is looking for; this thread is not regarding the nature of external memory! He wants to calc or find out a way to calc the max amount of DDR* memory needed for his application.

That is right. I am looking to estimate the required DDR memory, especially the required data bus bit width for my design.
For example assuming
- The input data rate is 6Gbps,
- DDR works with 1G clock,
- MIG can read/write into the DDR in 8 clock cycle.

Then :
To write 6Gb input to the ram I need at least 6*8*1 or 48 bit data bus.
If I want to write and then read, then I need to least double this bus width (i.e. 96 bits).


I don't know how many clock cycles MIG needs to read/write into the DDR memory.