FPGA to DDR connection

[aminpix]

It may look very basic question for you, I do apology.
It is my first time designing a FPGA board. This board has a Kintex FPGA and four DDR4 rams.
To connect the FPGA to the DDR memory, any specific pins of the FPGA I should choose (for DQ and ADD) or I can connect to any GPIO pins?

 

[KlausST]

Hi,

I guess you are not the first one connecting DDR RAM to KINTEX FPGA. Thus I expect the manufacturer provides informations as well as other internet sources.

Did you do a search at XILINX and in the internet?

Klaus

 

[FlyingDutch]

It may look very basic question for you, I do apology.
It is my first time designing a FPGA board. This board has a Kintex FPGA and four DDR4 rams.
To connect the FPGA to the DDR memory, any specific pins of the FPGA I should choose (for DQ and ADD) or I can connect to any GPIO pins?

Hello,

some connection lines for DDR memory are high-speed signals and them have to be designed (PCB) with length and impedance matching.

Best Regards

 

[aminpix]

Hi,

I guess you are not the first one connecting DDR RAM to KINTEX FPGA. Thus I expect the manufacturer provides informations as well as other internet sources.

Did you do a search at XILINX and in the internet?

Klaus

I searched Xilinx documents for XCKU15P-2FFVE1517. There are many document about DDR and Xilinx; but still I can't find any document specifying DDR4 pin can be connected to what pin of the FPGA.
For example DDR4_DQ[] can be connected to XXXX type GPIO.

However as @FlyingDutch pointed, not only the type of the pin is important, but also I should concern about the location of the pin.

any help?

 

[dick_freebird]

I believe that the address / data paths are LVDS-ish physical / electrical
but the termination voltage is VDD/2, not set by the driver common mode
control.

I'd start with the DDRx memory vendor's "what it wants" and then go wade
through the FPGA "what I/O resources you've got" looking for it (or as close
as you can get, and then figure out how to get any discrepancies blessed).

It would seem likely that somebody's gotten that all done and some IP
exists. Whether you can put your hands on it for free, well, ....

 

[FvM]

There are specific and detailed pin connection guidelines from Xilinx. All infos are collected on this site https://www.xilinx.com/support/docu...ltrascale-memory-interface-ddr4-ddr3-hub.html

DDR pin connection is very restricted, best you let the design tool decide.

 

[aminpix]

We plan to use DDRs for both microblaze and my custom logic design (PL).
Should I use two separate set of DDRs (two fly-by topologys) or only one set is enough and the developer can share the memories?

 

[dpaul]

Answering your original question, for DDR* memory interfacing, there are ALWAYS dedicated pins using which the MIG core interfaces with the external DDR*. Look at the Master Constraints File for the prototype board you are using. There in you can easily find which FPGA pins are the external memory interfacing pins.

Because of the above restriction (not a restriction in the real sense, but a design norn I would say), I have never seen an FPGA design which has 2 separate MIG cores and 2 separate sets of DDR* memories. You might use GPIO pins to interface with a set of DDR* memories. But then I can guarantee that meeting timing will be a nightmare.
So in my opinion, it is easier and better to manage if the FPGA logic can share one external DDR* memory and only 1 MIG core is used.