DSP slices in FPGA

[engr_joni_ee]

Hi, I am familiar with using dual port Block RAMs in Xilinx FPGAs. We usually generate the Block RAM IP Core in Xilinx Vivado and configure their ports, size and memory width etc. Then we instantiate the digital design to perform read/write operations between the digital design and the Block RAMs.

How do we work with DSP slices ? and do we also need to intentionally add in our design ? Do we also configure each DSP slice we need to add in our design and in what application we need to use DSP slices ?

 

[pbernardi]

Similarly to BRAM, you have two choices:

• Instantiate via primitive/IP, and configure your DSP ports, pipelines and functions manually.
• Instantiate via code/templates, and let the tool to instantiate the DSP for you.

Instantiating via IP is a bit more complicating than BRAM, you have to read and understand the DSP48 application note for your device, there are a lot of details to configure. But you may reach better performance/high frequencies if you do the correct configuration.

Instantiating via code is easier and more portable to other FPGAs. Basically, if you use a single multiply, the tool tends to use a DSP for integer multiplication. It is possible to describe pipelining and some constructs only by coding it, and the tool will probably recognize it, specially if you follow Xilinx templates. However, if your description is too complex, perhaps the tool cannot infer the DSP on the best way (for example, cascated DSPs with sum/multiplication/logic operation selected dinamically may be difficult to describe in a optimal way)

I suggest to look at DSP application note for yout specific FPGA (as example, for spartan 7: https://docs.amd.com/v/u/en-US/ug479_7Series_DSP48E1) and consult Vivado language templates on Tools/Language Templates.