How to instantiate another vhd file inside testbench, where the testbench is used for opening files

[metamisers]

I am trying to learn how to read from file in VHDL, the vhdl_code.vhd implements a low pass moving average filter, I already have a separate vhdl code Read_File.vhd that reads the data, now I have to read the column data from the file data2fpga.dat, and perform the low-pass operations in vhdl_code.vhd. My question is, should the Read_file.vhd should run as testbench or, how exactly i can perform this, i.e. how can I invoke the vhdl_code.vhd into Read_file.vhd?

Any guidance will be highly appreciated.

Thanks.

 

[metamisers]

The problem it seems is that ReadFile should be a testbench, but testbench should not have any components, hence ReadFile should be a component of a testbench I guess. How can I do that? Can anyone guide me?

 

[barry]

not sure why you think you need two files to read a file. in your test bench just implement the appropriate textio functions. And testbenches most certainly DO have components, how else would you test your code???

 

[metamisers]

My BAD, testbenches should not have entities, they must have components, I will update it immediately. Thanks for pointing it out!

Edit:

The problem it seems is that ReadFile should be a testbench, but testbench should not have any entities, hence ReadFile should be a component of a testbench I guess. How can I do that? Can anyone guide me?

 

[barry]

My BAD, testbenches should not have entities, they must have components, I will update it immediately. Thanks for pointing it out!

Edit:

The problem it seems is that ReadFile should be a testbench, but testbench should not have any entities, hence ReadFile should be a component of a testbench I guess. How can I do that? Can anyone guide me?

why don’t you just take the code from your readfile , and put it in your test bench? or, as you say, just instantiate readfile as a component? what don’t you understand about a component?

 

[metamisers]

@barry, I did as you said, i instantiated readfile as a component in a testbench, did the necessary generic & port mappings & was finally able to load the data into my filter! Thanks a lot for your help, "just instantiate readfile as a component?" This solved my problem!
Regards.

 

[Surah al Waqaih]

To integrate vhdl_code.vhd into Read_File.vhd, consider making Read_File.vhd the testbench. Instantiate vhdl_code as a component in Read_File.vhd and connect it to the data read from data2fpga.dat. Use appropriate signals or variables for communication. Ensure proper synchronization and simulate the testbench to validate your low-pass moving average filter implementation.