VHDL Testbench §§ Instantiation of entities

[Ilnheim]

Hello,
I´m fairly new at VHDL programming language and to the world of Digital Design and Verification and there are some concepts that I still didn´t fully understand.
Currently on my TB I have 8 components, being one of them the DUT.

I have a Testbench (already existing) with different component being instantiated (from different files), however if I take a look at the rtl I can see that for example:
Lets call it entity "X":

I have the ports assigned in the entity, then comes the architecture and then I create signals to connect to the ports.

However this X entity is instantiating other modules/rtl blocks:

example : inst_cpu_bus : entity work.cpu_inst


Now my problem is, I want to change or stimulate that work.cpu_inst entity on my TB. How can I do it?

How can I access the port of an instantiated block inside my DUT when in the TB I can only access the DUTs ports?


Sorry if the question is confusing, I can elaborate more if this is confusing.

 

[barry]

Yes, very confusing post.

There are ways to access lower-level signals, for example: https://www.doulos.com/knowhow/vhdl/vhdl-2008-easier-to-use/#hierarchicalnames

Also, you can just bring out signals in your ActiveHDL waveform and manually stimulate them.

But, I have to ask: if you want to stimulate a lower-level module, why aren’t you using a test bench for THAT module?

 

[Ilnheim]

Yes, very confusing post.

There are ways to access lower-level signals, for example: https://www.doulos.com/knowhow/vhdl/vhdl-2008-easier-to-use/#hierarchicalnames

Also, you can just bring out signals in your ActiveHDL waveform and manually stimulate them.

But, I have to ask: if you want to stimulate a lower-level module, why aren’t you using a test bench for THAT module?

So, in my project (DUT) we have a down-path and a up-path.
Currently we send specific data (read from a file) as an input to the down-path and we send random data as an input to the up-path.
The problem is that the random data being generated for the up-path didn't quite match a real case scenario so my job now is to fix that.

We came to the conclusion that the input of the up-path should be selected from the input of the down-path (which is read from a file) and not being random.

There is a block inside the DUT that has interfaces on both down-path and up-path and this block stores the down-path data. So I can select the data I want to use as an input to the up-path.

This block is the top hierarchy of 3 others blocks (one that splits the data, one that stores the data and one that chooses the flow of the data).

I want to access those 3 blocks, but from my main TB.vhd file I wasn't able to do it.
I'll check the link you sent me and I'll try some stuff out then I'll let you know if I was able to do it.

Quick noob question if you have the time and patient to answer:

On the TB when I add an component, let's say (block_demux_rd), it will initialize that components RTL (ports and architecture) right?
All I can do is, knowing the blocks ports and architecture from the rtl, stimulate it right?

 

[barry]

Not sure what you mean by “initialize that’s components RTL”. Do you mean apply default values to the inputs and outputs? The answer is no. You can do that in the VHDL, for example:

port (
IN1 : in std_logic := ‘0’;
IN2 : in std_logic := ‘1’;

 

[dpaul]

How can I access the port of an instantiated block inside my DUT when in the TB I can only access the DUTs ports?

If I have understood your question correctly, you need VHDL2008 to access any signal/port of an instantiated module from your TB.

• alias some_buried_sig is << signal top_module_inst.sub_module_inst.my_sig : std_logic_vector(3 downto 0) >>;

Search "vhdl 2008 hierarchical reference example"

 

[Ilnheim]

@barry
@dpaul
Sorry, it is my bad for not explaining correctly.

When I instantiate a component like this:

inst_block_x : entity.work.xblock

generic map (
..
..
);
port map (
..
..
);

Will I instantiate the component with the architecture defined in its rtl?

Or do I have to repeat what is being done in the rtl?

Thank you for your help guys.

 

[dpaul]

Syntax: mymodule_inst : entity work.mymodule(mymodule_arc)

mymodule - Entity name
mymodule_arc - Architecture name of the entity "mymodule"
mymodule_inst - Instantiation name
work - Name of the library

 

[barry]

Sorry, it is my bad for not explaining correctly.

When I instantiate a component like this:

inst_block_x : entity.work.xblock

generic map (
..
..
);
port map (
..
..
);

Will I instantiate the component with the architecture defined in its rtl?

Or do I have to repeat what is being done in the rtl?

Thank you for your help guys.

all you need is the instantiation as above. Why would you have to repeat the rtl? What would be the point of components then?
I think you need to educate yourself about VHDL, this is fundamental stuff.