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Recent content by eng.amr2009

  1. E

    Cadence NCSim RTL simulation signal skew

    Guys, I have a weird issue. I have an RTL where I delay a signal under clock process. It's a simple flop. When using NCsim I see the delayed signal is asserted in the same clock edge as the source signal. BTW : This issue does not occur with Questasim. My only doubt is that the source signal is...
  2. E

    [vhdl] define vector slice in package

    I found the solution. The range can be defined as follows : subtype frame_length_range is natural range 15 downto 13; Then I can index the vector with frame_length_range normally
  3. E

    [vhdl] define vector slice in package

    Hi guys, I'm implementing a certain packet decoder. The incoming packet is sliced according to certain ranges defined in a standard. I want to define the slice ranges in a package so that my code is readable and generic at the same time. For example if I'm slicing the control_field then I...
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    finding transfer function of simulink system

    Guys, I'm working on a filter design where the filter is modeled in Z-domain. I'm building the filter in simulink using basic elements and editing the fixed point data widths to prepare for RTL implementation. The problem is I do not know the rules to set the width of integrator output as the...
  5. E

    setting clock setup&hold uncertainity

    Thanks for your reply. But I'm aware of the setup & hold basics. I'm asking about the setup & hold clock uncertainty not the setup & hold for the flops. I can not relate them as the concept of clock uncertainty represents the skew between clock edges @ flop clock inputs. Is there any reason to...
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    setting clock setup&hold uncertainity

    Hi guys, I have been searching about the clock uncertainty and what I got is that it represents the maximum skew @ clock inputs of different flops for a given clock tree. If this understanding is correct kindly confirm. My question here is, what are the basis that I should use to be able to...
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    Modelsim -sdftyp, -sdfmax, -sdfmin

    Hi guys, I do not get the difference between the three mentioned switches in vsim command for SDF annotation. -sdfmin, -sdfmax, -sdftyp Let's take SDF for the typical extraction sdf_file_typical.sdf What is the difference between the following commands: 1) -sdftyp /dut=sdf_file_typical.sdf...
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    verilog tasks - output reg does not update

    Hi guys, I implemented some tasks in a separate file. Then I include these tasks in my test bench. The tasks have output ports. I call the tasks in initial block in test bench and connect the outputs of the tasks to reg types in the test bench. The problem now is that the registers in test...
  9. E

    Behavioral simulation of gate level - Modelsim

    Guys, In case I use a post APR or post Synthesis netlist in simulation without SDF annotation, I receive timing violations as the timing checks are performed based on default timing in standard cells behavioral model. I know of a modelsim option called +notimingchecks which is added to vsim...
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    sdf annotation issue - Cadence NCSIM

    Hi guys, I was running timing simulation using NCSim and due some issues the SDF annotation failed. However, I did not receive any timing violation as It happened before while using modelsim. Receiving violations is a sign that there are delay information. The delay info exists in the library...
  11. E

    behavioral clock gating & ICG

    Hi guys, I'm using latch based discrete clock gating module. The clock is active high and I sample the enable with an active low latch. So, I'm sure that the latched enable will never toggle @ the clock rising edge Questions: 1) Do I need to add clock_gating_check in synthesis constraint ...
  12. E

    Clock gating setup violation

    Hi guys, I'm using a behavioral clock gating module as follows Enable signal is retimed by a falling edge flop then the output of the flop gates the clock using an AND gate. All the flops driven by the gated clock are rising edge flops. I receive clock gating setup violation at relative to...
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    Clock gating, mux's and division - Cadence RC

    How can I define the relationship between them ? Could you provide an example ? In case I run synthesis without defining the relationship, what will be the effect on the resulting circuit ? - - - Updated - - - The two clocks input to the MUX are clk & clk/4 (clk divided by four) or in other...
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    Clock gating, mux's and division - Cadence RC

    Hi guys, Summary of Q's :D In cadence RC, upon clock gating, clock multiplexing or clock division, should I define the output clock from these modules in the synthesis script ? ---------------------- Detailed: I implemented a module with multiple clock inputs which I need to synthesize. say...
  15. E

    modelsim command line arguments

    Hi there, I was developing a TCL script for simulation with modelsim. The TCL script accepts some command line arguments like simconfig.tcl -coverage <value1> -toplevel <value2> -tc <value3> When I tried to run the script via tclsh under linux, it works perfect. As I actually need it for...
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