Clock gating setup violation

[eng.amr2009]

Hi guys,

I'm using a behavioral clock gating module as follows

Enable signal is retimed by a falling edge flop then the output of the flop gates the clock using an AND gate. All the flops driven by the gated clock are rising edge flops.
I receive clock gating setup violation at relative to clock rising edge at the input of the AND gate.
Following the path I found that tool fed the retiming flop by the clock from the clock network while the AND gate is fed by the clock directly.
Consequently, the delay until the enable signal is generated at the output of the retime flop includes the clock tree latency + clock to Q of the flop.
I'm using this gating module allover the design but I received the violation for this clock specifically as its frequency is high + high uncertainity of about 20% of the period.

Is there any missing options should I include in the CTS options ? Or in the synthesis before APR ?
I thought I can insert buffer to in the path from clock pin to the AND gated to insert some delay.
Is there any other solutions ?


I'm using cadence encounter for both synthesis and APR

Thanks

 

[sharath666]

Was expecting some expert to answer this...But...
Are you sure you need such a high uncertainty? The buffer delay has to be added between the and gate and the clock pin, not before the and gate..