eng.amr2009
Junior Member level 3
Guys,
I have a weird issue. I have an RTL where I delay a signal under clock process. It's a simple flop. When using NCsim I see the delayed signal is asserted in the same clock edge as the source signal.
BTW : This issue does not occur with Questasim.
My only doubt is that the source signal is comming from say clock_1 and the clock that I use to delay the signal is clock_1_g where clock_1_g is a gated version of clock_1. I suspect that delta value of the simulation.
The simulation resolution is much less than the required simulation time scale. The clock period is tens of nano second where the resolution is 1fs.
The simulation includes UVM environment, VHDL and Verilog RTL.
Is it a simulation option or what ? Any help ?
Thanks,
Best Regards,
I have a weird issue. I have an RTL where I delay a signal under clock process. It's a simple flop. When using NCsim I see the delayed signal is asserted in the same clock edge as the source signal.
BTW : This issue does not occur with Questasim.
My only doubt is that the source signal is comming from say clock_1 and the clock that I use to delay the signal is clock_1_g where clock_1_g is a gated version of clock_1. I suspect that delta value of the simulation.
The simulation resolution is much less than the required simulation time scale. The clock period is tens of nano second where the resolution is 1fs.
The simulation includes UVM environment, VHDL and Verilog RTL.
Is it a simulation option or what ? Any help ?
Thanks,
Best Regards,