Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Cadence NCSim RTL simulation signal skew

Status
Not open for further replies.

eng.amr2009

Junior Member level 3
Junior Member level 3
Joined
Dec 21, 2009
Messages
25
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Egypt
Activity points
1,509
Guys,

I have a weird issue. I have an RTL where I delay a signal under clock process. It's a simple flop. When using NCsim I see the delayed signal is asserted in the same clock edge as the source signal.
BTW : This issue does not occur with Questasim.
My only doubt is that the source signal is comming from say clock_1 and the clock that I use to delay the signal is clock_1_g where clock_1_g is a gated version of clock_1. I suspect that delta value of the simulation.
The simulation resolution is much less than the required simulation time scale. The clock period is tens of nano second where the resolution is 1fs.
The simulation includes UVM environment, VHDL and Verilog RTL.

Is it a simulation option or what ? Any help ?

Thanks,
Best Regards,
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top