Clock gating, mux's and division - Cadence RC

[eng.amr2009]

Hi guys,

Summary of Q's
In cadence RC, upon clock gating, clock multiplexing or clock division, should I define the output clock from these modules in the synthesis script ?
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Detailed:

I implemented a module with multiple clock inputs which I need to synthesize.

say I have clk1_in & clk2_in input to a clock mux. The mux output is clk_mux_out. Then clk_mux_out is gated to generate clk_mux_g.

Do I have to define all these clocks in the synthesis script ?

What I do is define all these clocks, assign them the same domain and clock frequency.

In case I want to make the constraint of one of these clocks tighter than others for as margin is it harmful regarding the clock to clock edge ?

In case I multiplex two clock of different frequencies, do I need to constraint the mux output to the fastest clock ?


I'm stuck at this

 

[jbeniston]

I'd say you should define clk1_in and clk2_in at the frequencies they are supposed to be... but, use the report_timing on a flip-flop clocked by the output of the mux and see what it is doing.

For clock dividers, use create_generated_clock. Whether you need to do anything for clock gating cells depends if you are using them to create a pulsed clock of a lower frequency, or are just gating the clock on or off.

 

[sharath666]

For your last question, I would say that you have to constrain your individual clocks and also define the relationship between them. For this scenario, they are logically exclusive..
I did not understand your 2nd last question.

 

[morris_mano]

In case I multiplex two clock of different frequencies, do I need to constraint the mux output to the fastest clock ?

if you define two clock inputs, then tool will automatically try to meet timing for both clocks as it can see through normal mux. If there is no timing path between those two clocks, you can set the false path between those two clocks.

If you have glitch free clock mux, then you will have to define clock on the glitch free mux output as tool doesn't see through glitch free clock mux. Yes, I would try to contraint the mux output to the fastest clock in this case.

 

[hoanglongroyal]

Do I have to define all these clocks in the synthesis script ?

--> yes, sure

In case I want to make the constraint of one of these clocks tighter than others for as margin is it harmful regarding the clock to clock edge ?

--> I dont understand the question

In case I multiplex two clock of different frequencies, do I need to constraint the mux output to the fastest clock ?

--> dont care about diff or same freq, 2 clocks are selected by MUX, then you have to set_clock_group them as logical exclusive. Synthesis tool will refer to both of clocks without any paths between them because of exclusive. if you want to choice the fastest clock, then you can set_case_analysis for S pin of MUX to choice the faster than.

 

[eng.amr2009]

For your last question, I would say that you have to constrain your individual clocks and also define the relationship between them. For this scenario, they are logically exclusive..

How can I define the relationship between them ? Could you provide an example ?
In case I run synthesis without defining the relationship, what will be the effect on the resulting circuit ?

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--> dont care about diff or same freq, 2 clocks are selected by MUX, then you have to set_clock_group them as logical exclusive. Synthesis tool will refer to both of clocks without any paths between them because of exclusive. if you want to choice the fastest clock, then you can set_case_analysis for S pin of MUX to choice the faster than.

The two clocks input to the MUX are clk & clk/4 (clk divided by four) or in other words one of the clocks is a generated clock from the other. Do I have to define clock group for them ? Knowing that they are assigned to the same clock domain.

 

[sharath666]

Just check up the syntax for the set_clock_groups command..In case you you don't define the relationship, you will get a sub optimal circuit or you may have to solve violations which don't exist in practice.

For your 2nd question, you will have to define the primary clock and the generated clock. You don't have to define a clock group for them..

 

[hoanglongroyal]

How can I define the relationship between them ? Could you provide an example ?
In case I run synthesis without defining the relationship, what will be the effect on the resulting circuit ?

- - - Updated - - -




The two clocks input to the MUX are clk & clk/4 (clk divided by four) or in other words one of the clocks is a generated clock from the other. Do I have to define clock group for them ? Knowing that they are assigned to the same clock domain.

1. in case, have no real path between clk1_in and clk2_in
set_clock_groups -logically_exclusive -group {clk1_in} -group {clk2_in}
2. you mean: create_clock clk1_in and generated_clock clk2_in source from clk1_in -div 4 , is that ?
--> still need to set_clock_group if have no read path between them

* if have no read path between them : have no paths before MUX.