verilog tasks - output reg does not update

[eng.amr2009]

Hi guys,

I implemented some tasks in a separate file. Then I include these tasks in my test bench. The tasks have output ports. I call the tasks in initial block in test bench and connect the outputs of the tasks to reg types in the test bench.

The problem now is that the registers in test bench do not get updated. However when I view the task internal signals I see them toggling !!!!
I do not know why the toggling signals in the tasks do not reflect to the port mapping in the test bench.

 

[dave_59]

In Verilog, task inputs are copied by value upon entry to the task, and task output are copied by value upon exit of the task. They are not like ports of a module.

SystemVerilog allows variables (not wires) to be passed by reference. That may give you the functionality you are looking for. See section 13.5 Subroutine calls and argument passing of the 1800-2012 LRM.