vcs compilation option "-file" does not work.

[coshy]

Does anyone have the same problem compiling with "vcs -file" in VCS?

Currently I am getting a keep compilation error message with "vcs -file" in vcs.

-file filename
Specifies a file that contains a list of path names to source files and required analysis options.
You can use this option to overcome the limitation of the -f option related to the compile-time options that begin with a minus(-) character.

I'm trying to compile with one ".vc" file which has included as the below

run.vc

+libext+.v
+incdir+../../../logical/cortexr5/verilog/
+incdir+../../../logical/models/cells/generic

-y ../../../logical/model/cells/generic

-v CORTEXR5_tcm_ram_test.v
-v CORTEX5_dummy_toplevel.v

After I run with "vcs -file run.vc", The error happened.

Error-[NSFG] No Source file given
No verilog source file is found from VCS command line and file list
specifiled with compilation option '-f'.
please check file list and note '//' is used for comment.
..


If I remember correctly, Cadence has no problem compiling in this way.
But Synopsys VCS does not work so well.
Did I something miss? What am I supposed to do?

 

[charchar123]

"VCS displays the Error-[NSFG] error message when you pass the library files with the -f option and if only -v is used inside the file. To resolve this error message, pass the design file in the file.list along with the library file. Passing only the library file with the -v option will not resolve the error."

solvnetplus.synopsys.com/s/article/Error-NSFG-No-source-file-given-Displayed-When-you-Include-the-f-Option-During-the-Elaboration-Phase-1576070087157