[SOLVED] Synthesis using Synopsys Design Compiler of Verilog Encrypted Source Code File (.vp file) that was generated using Synopsys VCS

[Kyrillos Magdi]

I am trying to synthesize using Synopsys Design Compiler a .vp file that was encrypted using Synopsys VCS simulation tool, it is a part of a large project where there are multiple RTL Verilog files and this is the only one that is encrypted and is integrated to the whole system, it ran very well on VCS and there were no compilation or simulation problems. I tried everything so that DC could read it and synthesize it along with the other RTL Verilog files but nothing worked with me. Anybody has an idea how could I make it work ?

 

[rr667]

Hello Kyrillos,
First of all, encrypted files are used all the time with IPs from different vendors; you can encrypt an RTL file of your choice and use it in both simulation and synthesis just to get a feel of how encrypted (or as Synopsys call them, protected) files are used.

Encrypted files are recognized by DC and VCS, just read them:

vcs top.v top_tb.v enc.vp
./simv

On encrypting a file, you are provided with plenty of options, to mention a few:
1- Encrypt only the body of the module (leave the module interface visible).
2- Encrypt the file to be only used within Synopsys tools.
3- Encrypt the file to be used only in simulation (say, a vendor wants to release an IP for simulation only and you need another license to synthesize it).

You must always ask if the encrypted file provided to you can be used "during synthesis" and "is it compatible with Synopsys tool".


Hope this made things a bit clear.

 

[Kyrillos Magdi]

Yes, thanks a lot