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Synopsys IC Compiler Verilog Parser Error

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jastor1329

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Hi

I am getting the following error while importing the netlist file to Synopsys IC Compiler:

"Module xr03d1 is not defined"
"Verilog Parser cannot parse the source file"

I have checked the link and target library files multiple times and have set up milkyway as well, still the error persists. Please help me in resolving this error.

Regards
 

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