Synopsys IC Compiler Verilog Parser Error

[jastor1329]

Hi

I am getting the following error while importing the netlist file to Synopsys IC Compiler:

"Module xr03d1 is not defined"
"Verilog Parser cannot parse the source file"

I have checked the link and target library files multiple times and have set up milkyway as well, still the error persists. Please help me in resolving this error.

Regards

 

[oratie]

Did you checked link_library (in addition to target library)?

 

[jastor1329]

yes, I checked both link library and target libraries