verilog/sv parser for instance signal connections

[davidpeng2023]

I wonder any suggestions for verilog/sv parser for multi-modules.

My task is to analyze the signal connection relationship in top module. To understand that, you can not just parse one module but multiple modules to know the input/output relationship. The tool like verible-verilog-syntax only works on one module and have no way to extract information like that.

I checked tools like Verilator or Yosys but it will take tons of effort to install and compile file hierarchy. Anybody had such experience before thus can suggest?

If yes, any python/perl wrapper of the tool for parsing work like this?

Thanks,
David

 

[gregbowers]

Hello

1. Pyverilog:
   • Python-based framework for Verilog/SystemVerilog analysis, supports parsing multi-modules.
2. MyHDL:
   • Python package for hardware description, has Verilog/SystemVerilog parsing capabilities.
3. Migen:
   • Python tool for digital design, supports Verilog code generation and analysis.
4. EDAPack:
   • Open-source EDA tools collection in Python, includes Verilog parsing.

For Perl, consider Verilog-Perl for Verilog parsing and hierarchy handling.