[SOLVED] Signal coming as undefined in verilog behavioral simulation

[bongosontan]

Hi, I am testing a verilog code which has the following structure:

reg a;
wire b;
always @(posedge clk) begin a <= b; end
wire c = a ^ 1 ;
assign b = c ^ 1 ;

But all a, b and c are coming as undefined in the behavioral simulation. This is a part of a bigger code, after debugging the signals one by one, I noticed that this part is causing the problem. 'c' never acquires a valid value. I have tried giving a, b and c some initial value also, same result. I am not understanding what is causing this error. It would be very helpful to hear some suggestions. Thanks in advance!

 

[ThisIsNotSam]

This is a good one
On real hardware, this would solve itself. But a simulator can't solve it because there is a circular dependency.
c=f(a) -> undefined because there is no reset for a
b=f(c) -> undefined because of c
a=f(b) -> undefined because of b at current clock cycle
---- next clock cycles comes
c=f(a) -> undefined because previous b was undefined
b=f(c) -> undefined because of c
a=f(b) -> undefined because of b

a simple reset would solve the issue

 

[bongosontan]

This is a good one
On real hardware, this would solve itself. But a simulator can't solve it because there is a circular dependency.
c=f(a) -> undefined because there is no reset for a
b=f(c) -> undefined because of c
a=f(b) -> undefined because of b at current clock cycle
---- next clock cycles comes
c=f(a) -> undefined because previous b was undefined
b=f(c) -> undefined because of c
a=f(b) -> undefined because of b

a simple reset would solve the issue

Thanks a lot. This indeed solves the issue.