Counting floating point for FSM design in Verilog

[aguntukbd]

Hi,
I am designing FSM for charging, discharging phases in inductor for AMS circuit. My counter works for integer numbers for different cycles. But in reality, it has to count floating point number or fractional numbers of fixed reference clock frequency depending on the different charging and discharging phases. How can I count upto a floating point number or fractional number? Should I use fixed point number in verilog? is there any simpler or efficient method? Your guideline or tips will be very useful!

PS: I am quite new to verilog & FSM design

 

[KlausST]

Hi,

in my understanding "counting" means: 1-2-3-4-5...

Do you mean "add up", "integrate" or "accumulate"?

you may add up floating point numbers like
0 + 1.2 = 1.2
1.2 + 0.9 = 2.1
2.1 + 1.7 = 8.8
...
Is this what you mean?

*******
Be careful when adding up in small steps on a large number. Like: 123456.789 + 0.001 does not work on single type floats.
I´d rather go with integers or fixed point.

Klaus

 

[aguntukbd]

Hi,

in my understanding "counting" means: 1-2-3-4-5...

Do you mean "add up", "integrate" or "accumulate"?

you may add up floating point numbers like
0 + 1.2 = 1.2
1.2 + 0.9 = 2.1
2.1 + 1.7 = 8.8
...
Is this what you mean?

*******
Be careful when adding up in small steps on a large number. Like: 123456.789 + 0.001 does not work on single type floats.
I´d rather go with integers or fixed point.

Klaus

I am not doing any arithmetic calculation like add, subtract, multiply etc...

I counting-down mainly. Suppose my counting goal is 20.35 times for the counter. How can I count from 20.35 to 0?

with integer counter I can easily count down by 1 whenever the condition fulfills. In this case how to do that?

 

[barry]

I am not doing any arithmetic calculation like add, subtract, multiply etc...

I counting-down mainly. Suppose my counting goal is 20.35 times for the counter. How can I count from 20.35 to 0?

with integer counter I can easily count down by 1 whenever the condition fulfills. In this case how to do that?

As Klaus tried to convey, counting means incrementing/decrementing by a fixed amount each step. You seem to want an adder(subtracter), NOT a counter. If you're "counting" to 20.35, what's your increment value? .01? .05?

 

[kaz1]

I am not doing any arithmetic calculation like add, subtract, multiply etc...

I counting-down mainly. Suppose my counting goal is 20.35 times for the counter. How can I count from 20.35 to 0?

with integer counter I can easily count down by 1 whenever the condition fulfills. In this case how to do that?

You seem to be counting clock periods. You cannot get fractions of your clock. What you need to do is have a faster clock e.g. 100 times faster to count to two decimals relative to reference clock.

 

[ThisIsNotSam]

Since you are new, you should definitely stay away from floating point. Learn how to build a simple FSM that counts clock edges using integer logic, that would already be a great start.

 

[KlausST]

Hi,

I still don´t understand....

Klaus

 

[dpaul]

I am not doing any arithmetic calculation like add, subtract, multiply etc...

I counting-down mainly. Suppose my counting goal is 20.35 times for the counter. How can I count from 20.35 to 0?

with integer counter I can easily count down by 1 whenever the condition fulfills. In this case how to do that?

I understand from the OPs post is that he has no idea regarding the incrementing/decrementing interval of the counter (is it 0.5, 0.1 or 1 or 2 or 5?).
Seems like he wants to either increment/decrement from a given value to a target value using an interval which is not fixed and needs to be calculated (e.g. decrement from 20.35 to 0)
If I have correctly interpreted this, then the OP needs another design that will 1st determine the interval steps between the start and target values. Once this is calculated this interval step value can be used to increment/decrement a counter. But then again the OP does not mention anything regarding factors using which the steps of increment/decrement between the start and target values may be calculated.
If I have understood correctly this is definitely not trivial to implement using floating point for a newbie.

 

[FvM]

Similar tasks are generally implemented as fixed point arithmetic in FPGA. It's simple and efficient.
Fixed point means you are using integer numbers with implied scaling factor.

For a detailed discussion you should describe the problem more clearly.

 

[Akanimo]

First, I don't think you really meant to mean floating point. That representation could also be for fixed-point. If you are saying "20.35 times", it may mean that you need an increment value of 0.05. ln other words, you need to generate a clock that is 1/0.05 times faster than your reference clock. It may also mean that you need to count your reference clock for 1/0.05 times. We can't say in this case what you need. You have the problem, it's only you that can give us a clue what solution you need. Then we can help you with the implementation.

 

[aguntukbd]

Hi all,

Thanks for your inputs, it seems like I made it more confusion by not clearing up fully which I did not think in the beginning was needed.

My clock period is fixed (200MHz) by the spec. It is a multi-ouput dc-dc where the inductor is charging and discharging using CCM algorithm. Now the FSM is part of the digital controller where it changes its states from charging phase to discharging phases (output is switch opening/closing) and stop. As the main vdd or power is coming from Li-ion battery the battery voltage is not fixed also like 3.7V nominal. Let’s say, it changes from 2.5V to 4.1 volts based on its charging/discharging situation. The peak inductor current is the charging phase and while discharging the inductor, the switches are on for different outputs. Therefore, the phases of charging-discharging will change after each cycle of charging-discharging of inductor finishes. Now as an example, for 2.5V of battery voltage the inductor charging phase can be 20.5 * clock period; for discharging phase, 1 switch may need to open for phase 10.35 * clock period, another switch can be 8 * clock period, another can be 1.346 * clock period and etc…. and for different battery voltages the phase for inductor to go to peak current will change and subsequently the discharging phases. Now how the phases are determined through feedback that is analog circuitry through comparators and so on which is not the concern of FSM.

The values of the phases are inputs for the fsm block. I designed the fsm which is running in simulation using integer values of phases and by counting down to zero from specific integer phase values. Now if the phase values are fractional, counting does not help, I am not sure what approach is easier and what approach is efficient to go further….

i realized that I cannot do counting here. Another thing if suppose one phase is 12.35, is that ok if I count till 12 and then how to go till extra 0.35? So, as I am new I am trying to implement in a way also which make sense and also efficient

 

[FvM]

At first sight, your PWM time resolution is limited to a clock period (under circumstances a half clock period utilizing DDR output register). Finer effective resolution can be achieved on average by dithering respective delta-sigma techniques.

You didn't yet refer to a hardware platform, thus we don't know if other resources for high resolution PWM are available.

 

[KlausST]

Hi,

still not clear.
A simple (had drawn) sketch will be a good idea to show what you mean.

I only can guess: Becaue no onw
You try the FPGA to generate a PWM which is ON (or OFF) for 10.35 clock periods.
If so: This is rather impossible. You can only have integer clock periods. In this case 10.

For sure one can imagine some fancy sub_clock period generating units ... but I can not recommend to do it this way.

Again: provide clear informations. Using sketches, signal flow, examples, timing diagrams ... because no one wants to waste time with guessing games.

Klaus

 

[aguntukbd]

I am not designing the FSM in FPGA. I am using 22nm technology and the circuit is analog-mixed signal (ASM) and I am using cadence virtuoso tool.

Here is the rough inductor charging discharging graphs and its corresponding switches which needs to be open and also the fsm state flow.

 

[KlausST]

Hi,

In the given pictures I see nothing related to the initial question about floating point.

I leave.

Klaus

 

[FvM]

O.k., user implemented digital logic rather than FPGA. Doesn't change much to the question.
How do you intend to implement switching events at fractional clock time? What is required timing resolution, what does it depend on?

 

[Akanimo]

So you intend to allocate variable time slots to each device you are discharging into with the time depending on the voltage level of any particular device. I guess, that is so all devices will be fully charged at the same time? And also the overall charging+discharging period is also variable and depends on the voltage level of the energy source?

 

[ThisIsNotSam]

I am not designing the FSM in FPGA. I am using 22nm technology and the circuit is analog-mixed signal (ASM) and I am using cadence virtuoso tool.

Here is the rough inductor charging discharging graphs and its corresponding switches which needs to be open and also the fsm state flow.

Are you designing digital logic in Virtuoso? Boy oh boy, talk about making your life hard!

 

[FvM]

The control concept described so far in this thread is based on synchronous digital logic ("Verilog FSM"). As discussed above, time resolution is limited by clock period, time intervals like 0.35 periods aren't feasible. You need to interpolate clock interval either by high frequency PLL clock or analog delay.

 

[aguntukbd]

So you intend to allocate variable time slots to each device you are discharging into with the time depending on the voltage level of any particular device. I guess, that is so all devices will be fully charged at the same time? And also the overall charging+discharging period is also variable and depends on the voltage level of the energy source?

The thing is the peak current of inductor will vary based on energy source and also different load values. So my switching time will be adjusted or better to say adapted. Therefore I have to make adaptive switching based on load and my inductor peak current and energy source. As I first had an idea of counting the value to zero for each phase (considering the integer value), my switching works by implementing counter by decrementing 1...

Now the problem is how to go on from here how can I count precision timing for fractional part? Keep in mind that it is just an fsm, the digital controller will give the values from analog parts. So I how switch will be open and close on that precision time or near precision time. My concern is that.

--- Updated Jun 14, 2024 ---

Are you designing digital logic in Virtuoso? Boy oh boy, talk about making your life hard!

The thing is the digital controller and fsm is just a part of the whole circuit, the rest of the circuit is analog. SO in turns it is analog-mixed signal circuit....

It is not a big digital ASIC design though this block eventually will be part of it....

--- Updated Jun 14, 2024 ---

The control concept described so far in this thread is based on synchronous digital logic ("Verilog FSM"). As discussed above, time resolution is limited by clock period, time intervals like 0.35 periods aren't feasible. You need to interpolate clock interval either by high frequency PLL clock or analog delay.

It is true it is limited by clock period. There is no PLL in the circuit, so that is out of the question. As I first had an idea of counting the value to zero for each phase (considering the integer value), my switching works by implementing counter by decrementing 1...

Now the problem is how to go on from here how can I count precision timing for fractional part? I can count till the integer value. When reach the fractional part, is there any way to come to the fractional part of the precision timing? You are saying to add each time delay when the fraction comes and add delay element to add it upto next integer value? In any case, I have to detect and process the fractional part. I am not sure how to process that fractional part in the fsm.

I know my starting question is not precise as where I started I did not know how to go on with the fraction at all. I am sorry for that