[SOLVED] SDC file

[prajapati_]

What is SDC (Synopsys Design Constraints) and what does it consists of? Can anyone explain this. I'm a lot confused.

 

[oratie]

First - define the clocks of your design and period of these clocks.
Second - define input/output delays of pins of your design.
And some other timing related constraints (multicycle, false path, max/min delay ...)

These constraints are needed for optimization of your design.

 

[aliarifat794]

SDC (Synopsys Design Constraints) is a format used to specify the design constraints for digital circuits during the electronic design automation (EDA) process. It is primarily used in the synthesis and timing analysis of digital designs. These constraints guide the EDA tools to optimize the design for performance, power, and area, ensuring that the final implementation meets the desired specifications.
Here is an article. I am not sure if you've checked it already.

https://signoffsemiconductors.com/introduction-to-sdc/#:~:text=The%20Synopsys%20Design%20Constraints%20%28SDC%29%20format%20is%20used,is%20based%20on%20the%20tool%20command%20language%20%28Tcl%29.

 

[dpaul]

@prajapati_
Google will answer your first question, there are 100s of explanations out there in the internet. So first let's see what homework you have done.

I'm a lot confused.

Regarding this, yes we might help, but you must elaborate your confusion!

 

[kirteshmiet]

What is SDC (Synopsys Design Constraints) and what does it consists of? Can anyone explain this. I'm a lot confused.

In simple words SDC contains clock definitions, exceptions ( false path, multicycle path ) and other timing constraints related information. Kndly elaborate your concerns so that more discussion can happen.

Timing Constraints
 Clock Definition (Time Period, Duty Cycle)
 Timing Exceptions (False Paths, Asynchronous Paths)

— Non-Timing Constraints
 Operating conditions
 Wire load models
 System interface, Design rule constraints (DRVs - Max. Cap./ Transition/Fanout)
 Area constraints, Multi-voltage and Power optimization constraints
 Logic assignments

 

[tr123]

SDC file is based on Tool Command Language (Tcl). This file is input to synthesis process and physical design process.
SDC will define your intent in term of various timing. You can guide synthesis tools and PD tools with the constraints. It is not guaranteed that all the constraints you specify will be met. EDA tools will not meet the constraints if they are aggressive. In that case you can relax a bit and re-run synthesis/PD. EDA tools will try to meet your constraints.
(Previous responses have explained in detail about all the constraints)