Is there a Chip level (more than 3 subsystems) Open Source RTL, SDC?

[Collang2]

I'm doing research on EDA, Physical design. and writing my paper
(I learned RTL design, but I have no design experience at Chip level...)

I am working on this project,,, so "comparison is required"
Existing methodology vs. proposed methodology

I need RTL and SDC of "chip with 3 or more subsystems."
There seems to be a lot of Subsystem's Open Source Code(Opencore, FPGAlearner) on the Internet, but I haven't found the RTL for "Chip-level" that incorporates it.
where should I find something like this RTL???

 

[ThisIsNotSam]

you are on the wrong track, I can tell you that.

but anyway, google OpenTitan. autosoc. MIT CEP.

 

[Collang2]

you are on the wrong track, I can tell you that.

but anyway, google OpenTitan. autosoc. MIT CEP.

Thank you for your answer! Do you have any advice?
My professor suddenly went to another school, so I haven't received any guidance these days

 

[ThisIsNotSam]

comparisons at SoC level are typically done only if you are implementing a floorplanning algorithm or global routing.

otherwise, 99% of the time you should be looking at individual blocks.