Positive edge-triggered flip flop does not work

[mohamis288]

I have implemented the Positive edge-triggered flip flop using the D-latch based diagram in cadence virtuoso.
For D-latch I have used the diagram in AckLP.png .
But it seems both edges are working.
What is the reason?

 

[crutschow]

But it seems both edges are working. What is the reason?

How fast are the edges (rise and fall times)?
They must be less than the circuit propagation delay.

 

[mohamis288]

How fast are the edges (rise and fall times)?

About 300us or lower. I have changed it. Nothing will change. The pulse width is 2.5ms.

 

[FvM]

Try ns rise time.

 

[crutschow]

About 300us or lower

That's way too slow, and it causing your problem.
As I said, the rise/fall times need to be less than the circuit propagation delay, which is likely in the low ns region.
Use a Schmitt-trigger to reduce the signal transition times.

 

[dick_freebird]

Question what "implemented" means. A DFF made of
verilog gates that have no delay, will fail because the
"hang time" is -too short- (0) and the DFFs need the
phase lag as "transient memory", to work. I have seen
this while building "structural verilog" views from transistor
level cell libraries. Delay properties or delay elements
had to be added.

The same may be true with too-slow-changing inputs
using SPICE modeled transistors but the question is
fundamental.

 

[manish12]

remove first inv from the diagram, and remove the inv from 2nd dff , and try

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