coshy
Member level 4
Dear All.
I've been trying to study about Design Compiler.
And I've done report with SDC TCL as the below
but one Timing Problem encounters when I add "set_load [expr [load_of $lib_name/an02d0/A1] * 15] [all_outputs]"
I want to know how to resolve this problem in real field if they add load but it makes Violation of Timing?
then I 've got a report as the below
I've been trying to study about Design Compiler.
And I've done report with SDC TCL as the below
but one Timing Problem encounters when I add "set_load [expr [load_of $lib_name/an02d0/A1] * 15] [all_outputs]"
I want to know how to resolve this problem in real field if they add load but it makes Violation of Timing?
Code:
set lib_name xxxxxx
current_design TOP
## Reset all constraints
reset_design
## Create clock object and set uncertainty
create_clock -period 2 [get_ports Clk]
set_clock_uncertainty 0.2 [get_clocks Clk]
## Set constraints on input ports
suppress_message UID-401
set_driving_cell -library $lib_name -lib_cell sdcfq1 [remove_from_collection [all_inputs] [get_ports Clk]]
set_input_delay 0.1 -max -clock Clk [remove_from_collection [all_inputs] [get_ports Clk]]
set_input_delay 1.2 -max -clock Clk [get_ports Neg_Flag]
## Set constraints on output ports
set_output_delay 1 -max -clock Clk [all_outputs]
set_load [expr [load_of $lib_name/an02d0/A1] * 15] [all_outputs]
then I 've got a report as the below
Code:
Startpoint: Neg_Flag (input port clocked by Clk)
Endpoint: I_COUNT/PCint_reg[2]
(rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: max
Point Incr Path
-----------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 1.20 1.20 r
Neg_Flag (in) 0.06 1.26 r
U157/ZN (nd02d1) 0.12 * 1.38 f
U164/ZN (nd02d2) 0.09 * 1.47 r
U180/ZN (invbd2) 0.05 * 1.52 f
U118/ZN (nd02d2) 0.06 * 1.57 r
U137/ZN (invbd4) 0.06 * 1.64 f
U88/ZN (nd02d1) 0.04 * 1.68 r
U178/ZN (nd03d0) 0.10 * 1.78 f
I_COUNT/PCint_reg[2]/D (dfnrq4) 0.00 * 1.78 f
data arrival time 1.78
clock Clk (rise edge) 2.00 2.00
clock network delay (ideal) 0.00 2.00
clock uncertainty -0.20 1.80
I_COUNT/PCint_reg[2]/CP (dfnrq4) 0.00 1.80 r
library setup time -0.08 1.72
data required time 1.72
-----------------------------------------------------------
data required time 1.72
data arrival time -1.78
-----------------------------------------------------------
slack (VIOLATED) -0.06