Command in Design Compiler to get least delay

[hw2000]

Hi Everyone,

I have a purely combinational logic that I want to synthesize. I want to get the least delay possible on this delay.
For that reason, I am using the following tcl script.

set search_path {./../benchmark/hyb_both/ \
                   /home/<redacted_path>/Nangate_45nm_libs/nangate/ \
                   /opt/coe/synopsys/syn/Q-2019.12-SP5-2/libraries/syn/ \
                   ./
                   }

set synthetic_library {Nangate.db dw_foundation.sldb}
set link_library {* Nangate.db dw_foundation.sldb }
set target_library {Nangate.db}

#======================================================
#  Global Parameters
#======================================================
set DESIGN "integer_add"
set delay 1.35

#======================================================
#  Read RTL Code
#======================================================
set hdlin_auto_save_template TRUE
analyze -f verilog ./integer_add.v
elaborate $DESIGN
current_design $DESIGN

#======================================================
#  Global Setting
#======================================================
set_load 0.05 [all_outputs]

#======================================================
#  Set Design Constraints
#======================================================
set_max_delay $delay -from [all_inputs]  -to [all_outputs]

#======================================================
#  Optimization
#======================================================
uniquify
check_design > hyb_both/Checking/$DESIGN\.check
set_fix_multiple_port_nets -all -buffer_constants
report_constraints -min_delay
compile_ultra

#======================================================
#  Output Reports
#======================================================
report_timing -max_paths 500000000 > ./hyb_both/Timing_overall/$DESIGN\.timing
report_timing >  ./hyb_both/Timing/$DESIGN\.timing
report_area >  ./hyb_both/Area/$DESIGN\.area
report_power >  ./hyb_both/Power/$DESIGN\.power
report_resource > ./hyb_both/Resource/$DESIGN\.resource

#======================================================
#  Change Naming Rule
#======================================================
set bus_inference_style "%s"
set bus_naming_style "%s"
set hdlout_internal_busses true
change_names -hierarchy -rule verilog
define_name_rules name_rule -allowed "a-z A-Z 0-9 _" -max_length 255 -type cell
define_name_rules name_rule -allowed "a-z A-Z 0-9 _[]" -max_length 255 -type net
define_name_rules name_rule -map {{"\\*cell\\*" "cell"}}
change_names -hierarchy -rules name_rule

#======================================================
#  Output Files
#======================================================
set verilogout_higher_designs_first true
write -format verilog -output Netlist/$DESIGN\_SYN.v -hierarchy
write_sdf -version 3.0 -context verilog -load_delay cell Netlist/$DESIGN\_SYN.sdf -significant_digits 6
write_sdc Netlist/$DESIGN\_SYN.sdc
#======================================================
#  Output Files
#======================================================
report_timing
report_area
report_power
report_resource
exit

I am changing the "delay" parameter by reducing it until the tool reports that Slack is violated. I currently don't want to add any non-idealities like load capacitance, input delay, output delay, etc. Can someone tell me if this is the right way to achieve what I want?

 

[glennramalho]

That I know there is no predefined way to get the smallest delay. You give the constraints and the tool will run until it matches all constraints or gives up. Then it stops. If the constraints are too easy it will finish quick. So, it will probably be keep on tighting it until it fails.

I remember some time back for on DC Infineon used to do something like this for area. They would synthesize the design, get the resulting area, then set_max_area to the result - 10% and then run the tool to reduce it even more.

Keep in mind that once you add your driver and load capacitance it will get a bit worse. And of course, keep in mind that this minimum delay does not come for free. The tool had to work harder to speed up the circuit. This could mean it used bigger buffers, perhaps duplicated some logic, perhaps use lower VT cells (if you have more than one VT library loaded), and then that could mean you gained speed but lost in area and power consumption.

 

[hw2000]

That I know there is no predefined way to get the smallest delay. You give the constraints and the tool will run until it matches all constraints or gives up. Then it stops. If the constraints are too easy it will finish quick. So, it will probably be keep on tighting it until it fails.

I remember some time back for on DC Infineon used to do something like this for area. They would synthesize the design, get the resulting area, then set_max_area to the result - 10% and then run the tool to reduce it even more.

Keep in mind that once you add your driver and load capacitance it will get a bit worse. And of course, keep in mind that this minimum delay does not come for free. The tool had to work harder to speed up the circuit. This could mean it used bigger buffers, perhaps duplicated some logic, perhaps use lower VT cells (if you have more than one VT library loaded), and then that could mean you gained speed but lost in area and power consumption.

So, my current process is the way to do it, right? Maybe I can also write a script that will reduce the delay by 10% until its not possible anymore.

 

[ThisIsNotSam]

Historically, it has always been like this with DC or with genus/RTL compiler. You try until the tool gives up by a few picoseconds. But wait, there is more!

Let's say you find a negative slack of -1ps after a few tries. This does not mean this is the absolute best delay you can get. If you push the tool harder, some different heuristics may still kick in and do different (more aggressive) optimizations. So in practice, if you want a clock period of 1ns, you could try to shoot for 700ps and then relax afterwards and see what you get.

Logic synthesis is a bit like dark magic. It is all heuristics.
There used to be a time when naming you registers differently would give better/worse results because the tools sorted potential solutions in alphabetical order