2-input gate count minimization in Design Compiler

[PanPapa]

Hello,

I am currently attempting to synthesize a circuit to correspond to a minimal And Inverter Graph (AIG).

That is, mapping with 2-input And/Or/Nand/Nor gates and inverters, my objective is to optimize the design to minimize the count of 2-input gates, considering inverters as free elements. This optimization goal differs from the traditional Nand2 cost, as it takes into account the potential improvements achievable by using inverters.

I'm interested in exploring whether Design Compiler can yield superior results compared to ABC in AIG minimization since it is ABC's native cost function for logical optimization. Specifically, I want to assess if Design Compiler can outperform ABC in optimizing the AIG node-count metric.

Could you provide any insights or recommendations on how to achieve this goal effectively?

Thank you for your assistance.

 

[BradtheRad]

Each software has a programmer in the offices who has in sight a goal for the software, and approaches it with his own method. Different programmers might use different techniques, depending on what is important to each programmer.

The optimization algorithm you speak of seems like it has more than one approach. Or more than one order to perform the steps of optimization. Or more than one list of steps to perform toward optimizing. Or more than one list of priorities needed to optimize.
Or spending a small length of time to optimize, versus a long period of time.

You'd need to question both programmers to discover their approach. They're liable to be unavailable to you for this.

To be thorough I believe it's best to use both softwares to explore your objectives, because you'll compare and combine their different results. One might emphasize an important factor to prioritize his results. The other might emphasize an equally important factor.

This optimizing function sounds like only a few programmers can tackle the problem. It requires (a) understanding what it means to achieve the goal, (b) expertise at devising code to perform the required routines.

 

[ThisIsNotSam]

starting point would be to perform synthesis in DC by limiting the use of complex gates and see what you get. but it is not a fair comparison, DC does not care about optimizing AIG count. DC is a multi-objective synthesis tool. it will do timing/area/power concurrently.