Gate level Simulation

[amansingh2704]

Can someone please explain me,
Why hanging condition occurs during Zero delay Gate level simulation?
How verification engineer fix this issue?
what can be some of the issue that can cause hanging simulation at GLS level?
Does this kind of hanging condition occurs at RTL level?
is ZDGLS simulation same as RTL simulation?

 

[dick_freebird]

"Structural verilog" won't express the "ballistic" behavior
of the tristate-inverter style DFF until you emulate the delay
of each inverter. Without this there is instant contention
when there should be a series of internal "handoffs" spaced
"just so".