Gate level simulation issue on questasim

[Farah Adel]

I want to simulate the net list on questasim. The design has ROMs. I want the simulator to see the db format of the memories because when i compile the gates of the technology and simulate the test bench with the net list, it produces an error that the memories are not defined. The following are 2 screenshots one after compiling the gates of the technology and when with the error appearing.

 

[barry]

You’re apparently missing the ROM module in your compilation.

 

[ThisIsNotSam]

most likely the memory provider has given you a simulation model of the memory. you have to use it together with your tb.

 

[rca]

most likely the memory provider has given you a simulation model of the memory. you have to use it together with your tb.

And to complete "ThisIsNotSam", this model can be populated by your ROM C code compile and modify in the correct format.