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Recent content by ywguo

  1. Y

    SDF annotation and a flatten netlist (schematic)

    Hi my2817, You said that my SDF file is in hierarchy format. I thought it was in flatten format because there is back slash "\" leading the slash "/". Is it correct? Yawei
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    SDF annotation and a flatten netlist (schematic)

    Hi Guys, I have a flatten schematic, imported from a flatten verilog netlist. To speed the ams simulation, I want to annotate SDF. However, it always reports the following Warning info. It seems that ams simulator does not find the instance in my flatten neltist. Tools version are irun(64)...
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    Choose a device in synplify

    Hi Guys, I try to implement my RTL design in an Altera device using Synplify. I click new Impl.... button on the GUI. However, there are only Xillinx devices in the device tab. I look at the installed directory. In the lib subdirectory there are definition for Xillinx, Altera, Cypress, Lattice...
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    Formality RTL vs. netlist

    formality rtl Hi, Kiran, Yes, the implementation has less registers because some registers are always assigned a constant in the RTL code. How do I set a contstant propagation? Thanks Yawei
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    Formality RTL vs. netlist

    Hi, Guys, RTL vs. netlist verification failed using Formality. I checked the RTL code and synthesized netlist. Actually, the netlist was right. The fail is just because that some registers and gates are reduced that were always '0' or '1'. How can I solve this problem? Thanks Yawei
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    Formality RTL vs. netlist

    compile_seqmap_propagate_constants Hi, Guys, RTL vs. netlist verification failed using formality. I checked the report and netlist, RTL code. Some registers and logics gates are reduced because the register was always '0' or '1'. The reduction didn't affect the function. How do I write the...
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    Remove assign statements in synthesize netlist

    Mission Complished. :D Thanks.
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    Remove assign statements in synthesize netlist

    Hi, Guys, How to remove assign statements in synthesized netlist? Some Astro versions do not allow assign statements in verilog netlist. In Advanced ASIC Chip Synthesis, it states that the following command should be set in a script. verilog_no_tri = true set_fix_multiple_port_nets...
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    Altera Stratix I/O configuration

    Hi, I am usign Altera Stratix DSP S80 Development Board. It has a dual seven-segment display, a Stratix EP1S80B956C6 device, and many other devices on board. After I programming the FPGA, the dual seven-segment display turns on/off ramdomly. When I press the reset switch on the board, the...
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    Formality stops, never finish

    Hi, I ran rtl vs. netlist formal verification using formality. It had never finished. It always stopped at status verifying. The design contains many multipliers and adders. I had even set some blocks as black box to reduce the complexity. It stopped at status verifying after more than 10...
  11. Y

    ATPG and post-layout simulation

    Hi, dr_dft, 4 days ago, I just wrote out a scan reordered netlist from the place and route tool, but ATPG cannot find the scan chain. So I tried to use the flow that I described above. Thanks Yawei
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    ATPG and post-layout simulation

    Hi, I used the scan chain reordering flow introduce by synopsys. At last, I found design compiler didn't reorder the scan chain as that in the place and route tool. According to that flow, design compiler should reorder the scan chain after place and route as that in the place and route tool...
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    ATPG and post-layout simulation

    scan reorder after cts Hello, I designed a chip with scan chain. The Place and route tool generated a scan order file to instruct design compiler to reorder the scan chain. Then design compiler exported netlist to TetraMax. We ran ATPG and generated test patterns. Simulations with the test...
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    Z state, Is it a software bug or a fault of the circuitry?

    Re: Z state, Is it a software bug or a fault of the circuitr Hello, I simulated a gate-level netlist with SDF annotation from layout using LDV 3.4 for LINUX. It showed Z state from a few registers at the waveform, although the simulation proved that the circuitry worked fine. First I...
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    Disable timing check in NC-Verilog

    negative timing check Hi, Ajeetha, Thanks very much. I really need to prevent the X state propagation. I try the option -nonotifier for ncelab. Now it doesn't shown any timing violation and X state at the waveform. Yawei
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