ywguo
Junior Member level 2
scan reorder after cts
Hello,
I designed a chip with scan chain. The Place and route tool generated a scan order file to instruct design compiler to reorder the scan chain. Then design compiler exported netlist to TetraMax.
We ran ATPG and generated test patterns. Simulations with the test patterns and synthesized netlist proved that the scan chain was right. But simulations with the test patterns and post-layout netlist failed.
Are you experienced with DFT design? Any comments are welcome.
Thanks
Yawei Guo
Hello,
I designed a chip with scan chain. The Place and route tool generated a scan order file to instruct design compiler to reorder the scan chain. Then design compiler exported netlist to TetraMax.
We ran ATPG and generated test patterns. Simulations with the test patterns and synthesized netlist proved that the scan chain was right. But simulations with the test patterns and post-layout netlist failed.
Are you experienced with DFT design? Any comments are welcome.
Thanks
Yawei Guo