ATPG and post-layout simulation

[ywguo]

scan reorder after cts

Hello,

I designed a chip with scan chain. The Place and route tool generated a scan order file to instruct design compiler to reorder the scan chain. Then design compiler exported netlist to TetraMax.

We ran ATPG and generated test patterns. Simulations with the test patterns and synthesized netlist proved that the scan chain was right. But simulations with the test patterns and post-layout netlist failed.

Are you experienced with DFT design? Any comments are welcome.


Thanks

Yawei Guo

 

[joe2moon]

scan chain ordering is done after cts

>> Simulations with synthesized netlist passed...
>> Simulations with post-layout netlist failed....
-----------------------------------------------------------------
At first, you should know the difference of these 2 simulation runs.

For example, what kind of options have been used during those simulations ?

During the simulation w/ synthesized netlist, maybe you used unit-delay or zero-delay, and do not turn-on timing checks.

While simulation w/ post-layout netlist, maybe you have annotated a SDF file.
------------------------------------------------------------------

Secondly, make sure your post-layout netlist is STA clean in the scan mode.

Especially, no hold time violations are allowed.
-------------------------------------------------------------------

Hope above ideas may help more or less

 

[sam31]

Hi,

There is timing violation?

 

[ywguo]

Hi,

I used the scan chain reordering flow introduce by synopsys. At last, I found design compiler didn't reorder the scan chain as that in the place and route tool. According to that flow, design compiler should reorder the scan chain after place and route as that in the place and route tool.

Before place and route, design complier writes the following.

dc_shell> set_scan_configuration -prtool avant
dc_shell> write_layout_scan -out design.def -noclockdomain
dc_shell> write -f db -hier cpu -out mydesign.db
dc_shell> write -f verilog -hier cpu -out mydesign.v

In Apollo, I detached the scan chian before preplacement, then connected that scan chain and optimized it after CTS.

Writes out the new scan reorder file
dbDumpScanChain (geGetEditCell) "scan.rpt"

After place and route, design compiler read the

dc_shell> set_scan_configuration -prtool avant
dc_shell> set_scan_configuration -prfile scan.rpt
dc_shell> set test_dont_fix_constraint_violations true
dc_shell> insert_dft -ignore_compile_design_rules

Do you have any comments?

Thanks for your kindful help.

Yawei

 

[dr_dft]

Yawei,

Is there any reason why you can't just write out a scan-reordered netlist from Apollo, and use that for your ATPG and post-layout sim?
Why do you need to go back to design-compiler?

 

[ywguo]

Hi, dr_dft,

4 days ago, I just wrote out a scan reordered netlist from the place and route tool, but ATPG cannot find the scan chain. So I tried to use the flow that I described above.


Thanks
Yawei

 

[dr_dft]

Ywguo,

Sounds like your problem is in the post-layout netlist produced by Apollo. Is it possible that Apollo did not do the reordering correctly?
What error/warning messages did you get when you try to run ATPG with the postlayout netlist?

 

[szwxxy]

Ywguo,

Sounds like your problem is in the post-layout netlist produced by Apollo. Is it possible that Apollo did not do the reordering correctly?
What error/warning messages did you get when you try to run ATPG with the postlayout netlist?

STA check in PT correct?
maybe check your timescale when simulation.