Z state, Is it a software bug or a fault of the circuitry?

[ywguo]

Re: Z state, Is it a software bug or a fault of the circuitr

Hello,

I simulated a gate-level netlist with SDF annotation from layout using LDV 3.4 for LINUX. It showed Z state from a few registers at the waveform, although the simulation proved that the circuitry worked fine. First I suspected it was a bug of the waveform display. Then I printed the register value using $diaplay. It was Z state, too. The Z state didn't propagate to the next register. For eg., in a shift register, the 26th register was Z, but the 27th register had never capture a Z state from the 26th register.

I am really confused. Any comments are welcome.


Thanks.

Yawei

Added after 37 minutes:

Hi,

I found it is a fault by myself. After optimization of the PR tool, the netlist had changed a little. Some ports and signals changed, but the declaration for the original wires are still there and become hi Z when simulation.


Thanks
Yawei

 

[sandysuhy]

Re: Z state, Is it a software bug or a fault of the circuitr

Hi ywguo,
Z : a floating value, a signal not driven by any component.It is an high impedance state. for eg:
if enable of tristate inverter is not active then output will be Z i.e., the output pin is not driven by any component.
Was it help full.

Good Luck.