What is delay cell? Is it just big buffer?

[Collang2]

Hello,

What is the DLY Cell?

1) Just BUF-BUF-BUF-BUF…chain?
2) INV x 2 chain?
3) Or it is just big buffer with huge RC value?


When there is no area limit no SI limit, can you insert a large amount of delay cell chain for a large hold violation fix?

 

[D.A.(Tony)Stewart]

https://chat.openai.com says...


The term "DLY cell" likely refers to a delay cell, which is a fundamental building block in digital circuits used for introducing a controlled delay in a signal path. The specific structure of a delay cell can vary based on the design requirements and technology used. Here are a few possibilities:

1. BUF-BUF-BUF Chain:
   • This is a common approach where a series of buffer (BUF) stages are connected in series to create a delay chain. Each buffer stage introduces a small delay, and the cumulative delay is controlled by the number of buffers in the chain. This method is simple and effective for creating controlled delays.
2. INV x 2 Chain:
   • Another approach involves using inverters (INV) in a chain. In this case, the delay is introduced by the propagation delay of the inverters. Using two inverters in series can create a delay element, and the cumulative delay can be adjusted by the number of inverters in the chain.
3. Big Buffer with Huge RC Value:
   • A delay cell could also be implemented using a larger buffer with a significant RC (resistance-capacitance) time constant. The RC time constant determines the rate at which the voltage across the capacitor changes, affecting the delay introduced by the buffer. This approach might be used for larger delays where precise control is required.

The choice between these methods depends on the specific requirements of the design, including the desired delay resolution, power consumption, area constraints, and the technology used in the fabrication of the digital circuit.

It's worth noting that in digital design, delay cells are often used for various purposes, including clock domain synchronization, phase-locked loops (PLLs), and other applications where controlled delays are essential. The exact implementation details of a delay cell can vary between different technologies and design methodologies. The specific usage and requirements in a given context would determine the most suitable type of delay cell to be used.

...
All simple BUF's are inverting. So be sure to use the correct phase or edge of the clock for sync.
In some cases, there might be alternative solutions, such as restructuring the logic or optimizing the critical path