Formality RTL vs. netlist

[ywguo]

Hi, Guys,

RTL vs. netlist verification failed using Formality. I checked the RTL code and synthesized netlist. Actually, the netlist was right. The fail is just because that some registers and gates are reduced that were always '0' or '1'.


How can I solve this problem?



Thanks
Yawei

 

[yln2k2]

Hi ,

I am not sure .
But if you have some floating I/P when you instantiated a module , DC by default drive 0 . Please make sure you don't have any floating I/P .


Thanks & Regards
yln

 

[wakaka]

looks like DC optimised ur netlist.
Try to use set constant 0/1 to the required pins to make the formality pass.

 

[rameshsuthapalli]

Hi All,

please write out the svf file while doing rtl synthesis and read that svf file in the formality and do the verification then formality will pass becuse tool try to map the design according to the name of cell/net in the both rtl and netlist. svf will give the naming change that has taken place in the rtl cell/net names in the rtl while converting it to the netlist.

Regards,
Ramesh.S

Added after 1 minutes:

or use the following commands in the formality.

match
match -heir
match -datapath

Regards,
Ramesh