Remove assign statements in synthesize netlist

[ywguo]

Hi, Guys,

How to remove assign statements in synthesized netlist? Some Astro versions do not allow assign statements in verilog netlist.

In Advanced ASIC Chip Synthesis, it states that the following command should be set in a script.

verilog_no_tri = true
set_fix_multiple_port_nets -feedthroughs
set_fix_multiple_port_nets -all -buffer_constants

I follow the above rule. It failed.

Any help is welcomed.


Thanks
Yawei

 

[johnma]

I resolve this problem by define new naming rules before writing netlist out. Just like this : define_name_rules verilog -remove_internal_net_bus -equal_ports_nets.
Also you need the set_fix_multiple_port_nets -all -buffer_constants .
Good luck!

 

[ywguo]

Mission Complished.

Thanks.