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Recent content by steven852

  1. S

    Doubt about reset implementation in Verilog

    Hi, I am looking at this reset implementation and have a big doubt: always @(posedge clk or negedge reset1 or negedge reset2) begin if (!reset1) begin // reset a set of registers to value set 1 end else if (!reset2) begin // reset the same set of registers to value set 2...
  2. S

    The simplest way for doing indexing in Verilog

    Hi, I have an indexing question in Verilog. For instance, a set of parameters are defined as paramter [7:0] COMM0 = 8'h00, COMM1 = 8'h01, COMM2 = 8'h02, COMM3 = 8'h03, COMM4 = 8'h05...
  3. S

    Sample Makefile for SystemC compilation

    Can someone share sample Makefiles for systemC compilation? I have downloaded and installed SystemC and want to know if some has developed a compilation/viewing flow with SystemC. I don't quite understand the ones coming with SystemC package, for example, what if I want to change to other...
  4. S

    Looking for docs about high speed IO protocol

    Re: High speed IO protocol yes, including signaling systems: lvds, cml, etc
  5. S

    signaling spec introduction

    Hi, Where can I find introduction materials on digital signaling specifications (LVDS, ECL, etc)? Thanks
  6. S

    What is the most efficent digital delay line out there?

    Re: digital delay line Hi, Besides area and power, the delay line should have less uncertainty (this is mainly a library issue but architect also plays a roll). Do you have references on this? Thanks
  7. S

    conditional assignment statement

    Think this in more hardware way: When see a rising edge, then a mux is created, i.e., the control line of the mux is also determined by the rising edge.
  8. S

    Why code a state machine like this?

    It may relate to reducing glitches in the state machine. But I just don't see how it works. In fact, I think it is a waste to increase # of bits in the state coding in this particular implementation.
  9. S

    Why code a state machine like this?

    Hi, I just saw a way to code a 4-state machine like this: parameter s0= 8'b00000000, s1= 8'b00010000, s2= 8'b00100001, s3= 8'b00110000, s4= 8'b01000000, s5= 8'b01010100, s6=...
  10. S

    generate in Verilog 2001

    Hi, What is the benefit in using generate/endgenerate in Verilog 2001? It seems can't be simulated without going to elaborate process. Thanks
  11. S

    What is the most efficent digital delay line out there?

    digital delay line Hi, What is the most efficent digital delay line out there?
  12. S

    What tool can generate a pdf file for Physical Compiler?

    pdef compare Hi, What tool can generate a pdef file for Physical Compiler? By the way, how to compare Physical Compiler P&R results with other tools, e.g., SoC Encounter? Thanks
  13. S

    What is port swapping and why is it done for reducing delay?

    Re: encounter How to do and manage port swapping? I mean if it is possible to fix part of the IO ports while let Encounter take care the others? Thanks
  14. S

    Help:about perl script

    Oops, sorry I misunderstood the question. I may ask this question next time.
  15. S

    What to do if post layout timing not matching to synthesis

    Re: What to do if post layout timing not matching to synthes I agree with what stevepre and au_sun said and this is what we've practised. But one thing I am not sure: after many tries, how to tell that the P&R tool cannot make it so that refloorplanning, resynthesis or re-coding is needed. I...
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