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Doubt about reset implementation in Verilog

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steven852

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Hi,

I am looking at this reset implementation and have a big doubt:

always @(posedge clk or negedge reset1 or negedge reset2) begin
if (!reset1) begin
// reset a set of registers to value set 1
end
else if (!reset2) begin
// reset the same set of registers to value set 2
end
else begin
// normal state machine
end
end

The first problem is that I think synthesis only take one "or" in the always list. The second one is that how this implementation could be realized in hardware. There may be race condition between reset1 and reset2 but I am more worrying about the circuit. The third one is whether a better solution is available.

Thanks
 

wangkl

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Re: Reset in Verilog

The first problem is that I think synthesis only take one "or" in the always list.
[Comment: synthesis could take more]

The second one is that how this implementation could be realized in hardware.
[It depends on your target library. In such case, u need DFF with both async set and async reset]

There may be race condition between reset1 and reset2 but I am more worrying about the circuit.
[Yes, such code will always lead race. we need firstly confirm which one has higher priority, reset1 or reset2. Secondly, we need at least two types DFF,
one is that DFF with async set higher priority than async reset, and another is that DFF with async reset higher priority than aysnc set. Finally, the synthesis tool should be smart enough to implement such priority]

The third one is whether a better solution is available.
[Not sure]


=====================================

module async_reset_1_2 (
clk,
async_reset1_b,
async_reset2_b,
d,
q
);

input clk, async_reset1_b, async_reset2_b;
input[3:0] d;
output[3:0] q;

reg [3:0] q;
always@(posedge clk or negedge async_reset1_b or negedge async_reset2_b)
begin
if (!async_reset1_b)
q <=4'b1010;
else if (!async_reset2_b)
q <=4'b1100;
else
q <= d;
end

endmodule


===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 1 | N | N | N | Y | N | N | N |
| q_reg | Flip-flop | 2 | N | N | Y | Y | N | N | N |
| q_reg | Flip-flop | 1 | N | N | Y | N | N | N | N |
===============================================================================

module async_reset_1_2 ( clk, async_reset1_b, async_reset2_b, d, q );
input [3:0] d;
output [3:0] q;
input clk, async_reset1_b, async_reset2_b;
wire n1, n2, n3, n7;

sdffprs q_reg_1_ ( .ck(clk), .d(n1), .q(q[1]), .rb(n2), .sb(
async_reset1_b), .sdi(d[1]), .se(n3) );
sdffprs q_reg_2_ ( .ck(clk), .d(d[2]), .q(q[2]), .rb(async_reset1_b),
.sb(async_reset2_b), .sdi(n1), .se(n1) );
sdffps q_reg_3_ ( .ck(clk), .d(d[3]), .q(q[3]), .sb(n7), .sdi(n1),
.se(n1) );
sdffprq q_reg_0_ ( .ck(clk), .d(d[0]), .q(q[0]), .rb(n7), .sdi(n1),
.se(n1) );
tielow U10 ( .x(n1) );
tiehigh U11 ( .x(n3) );
and2 U12 ( .a(async_reset1_b), .b(async_reset2_b), .x(n7) );
nand2i U13 ( .a(async_reset2_b), .b(async_reset1_b), .x(n2) );
endmodule

=========================================

To avoid simulation mismatch between netlist and verilog.
Please use following style:

module async_reset_1_2 (
clk,
async_reset1_b,
async_reset2_b,
d,
q
);

input clk, async_reset1_b, async_reset2_b;
input[3:0] d;
output[3:0] q;

reg [3:0] q;

// we assume async_reset1_b has higher priority than async_reset2_b
wire masked_async_reset2_b = (~async_reset1_b) ? 1'b1 : async_reset2_b;
always@(posedge clk or negedge async_reset1_b or negedge masked_async_reset2_b)
begin
if (!async_reset1_b)
q <=4'b1010;
else if (!masked_async_reset2_b)
q <=4'b1100;
else
q <= d;
end

endmodule
 

laglead

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Re: Reset in Verilog

Synthesis only take one "or"
 

darylz

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Reset in Verilog

pls note the dff in your lib, there is only one reset pin? also you need to refer to the code style guide from synthesis toools
 

incisive

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Re: Reset in Verilog

synthesis tools take one reset, other used goes to race condition. Set the priority and use the other reset in the state machine i.e if x = 1 reset state else st machine.
and in the combo part, if x2 = 1 then go to x2 state and dump the required values so that it is in that state when x2 is there.
 

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