sree205
Advanced Member level 1
Hi,
can we use the conditional assignment statement inside always blocks like the example below ??
module ex(clk,x,a,b,y)
input a,b,x;
output y;
reg y;
always@(posedge clk)
y = x ? a : b ;
endmodule
can we use the conditional assignment statement inside always blocks like the example below ??
module ex(clk,x,a,b,y)
input a,b,x;
output y;
reg y;
always@(posedge clk)
y = x ? a : b ;
endmodule