conditional assignment statement

[sree205]

Hi,
can we use the conditional assignment statement inside always blocks like the example below ??

module ex(clk,x,a,b,y)
input a,b,x;
output y;
reg y;

always@(posedge clk)
y = x ? a : b ;

endmodule

 

[Shurik]

It wrote not correctly!!!

assign in always not use!!!!

need write:
OR
assign y = x ? a : b ;

OR

always@(posedge clk)
if (x)
y = a;
else
y = b ;

OR

always@(posedge clk)
case (x)
1'b1 : y = a;
1'b0 : y = b ;
endcase

 

[aji_vlsi]

Hi,
can we use the conditional assignment statement inside always blocks like the example below ??

module ex(clk,x,a,b,y)
input a,b,x;
output y;
reg y;

always@(posedge clk)
y = x ? a : b ;

endmodule

That should work. Did you see any issues?

Ajeetha, CVC
Contemporary Verification Consultants Pvt Ltd. http://www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar

 

[steven852]

Think this in more hardware way:

When see a rising edge, then a mux is created, i.e., the control line of the mux is also determined by the rising edge.

 

[shiv_emf]

may b its nt synthesiable

 

[aji_vlsi]

may b its nt synthesiable

AFAIK, it is perfectly synthesizable.

Ajeetha,CVC
* New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Using PSL/SUGAR
Design Verification Consultant,
Contemporary Verification Consultants Private Limited,
Bangalore, India, http://www.noveldv.com

 

[sree205]

hi aji, you are absolutely right. its synthesizable and its easy on the eyes while debugging.

 

[ramana_k22]

Above code simulates and synthesizes
regards,
ramana

 

[nipoon]

in assign statement
lhs is continuously assigned
but if we use it in an always block
it is a crime because , always block will be executed only at athe posedge of an event hence we may miss the values

 

[brotherjam]

yes, you can do this like this.
it is a mux followed a register.

 

[beta0]

hi aji, you are absolutely right. its synthesizable and its easy on the eyes while debugging.

yes, it's absolutely synthesizable.but , this kind of coding style may not acceptably
in many company.
useing the noblocking assignment would be a good choice when you need a dff.

 

[its_thepip]

it is sythenesizable