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Hi Steven,
Can you please clarify the term efficient i.e. in terms of power, area or speed ?
If you search in literature there are alot of techinques and each of them focus on either optizising time for a given area or minimum power for given timing.
I do not have any material which can be posted in this regard but IEEE has lot of papers which deals which tapper buffer optimization etc.
Besides area and power, the delay line should have less uncertainty (this is mainly a library issue but architect also plays a roll). Do you have references on this?
It is depends on the purpose of Degital delay .
If you want to use Delay for CLK ( in DDR ?) then it should be more accurate and should not change with PVT ( which means delay value should immune to process corners .) ...
If your question is how to create dll then i don't know the same .
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