[SOLVED] What are the steps that semiconductor companies perform to design digital ASICs from scratch?

[unixdaemon]

I am familiar with some steps, but I only worked in EDA software companies, and not in companies actually developing ASICs.

My understanding is that the following steps are involved:
1. Specification is developed and approved
2. Verilog is written
3. Verilog is simulated (ex. Verilator)
4. The hardware compiler is run (possibly in steps), which brings it to GDSII/OASIS (ex. Synopsys Fusion Compiler).
5. AI framework is engaged to choose best hardware compiler options (ex. Synopsys DSO.ai)
6. Formal and static verification is run on Verilog to find logical errors (ex. Synopsys VC Formal, Synopsys SpyGlass).
7. RC extraction is performed on the result of the hardware compiler run (ex. Synopsys StarRC)
8. Timing verification is done using Verilog, RC, SPICE models from the library (ex. Synopsys PrimeTime)
9. DRC is performed
10. Corrections are made based on timing, parasitic, DRC violations, and the hardware compiler is re-run on the corrected design.
11. Verification of design equivalence (ex. Synopsys ESP)
12. Mask generation for subsequent submission to the fab

The above steps are likely incomplete, because they are based on my EDA experience, not on real semiconductor development experience.

What is the complete set of actual steps that companies like Qualcom, NVidia, AMD, Apple perform in order to get from RTL to Fab?
The above companies seem to do things right, and, as I've heard, Qualcom didn't have any manufacturing failures in many years because they do things right.

Is there a diagram showing the complete workflow visually?

(I know that Synopsys and Cadence have some diagrams, but they are mostly from their marketing departments, and are very incomplete and sketchy.)

 

[dick_freebird]

A pure play foundry does not touch the ASIC design,
only provides cell libraries, data and rules to enable a
customer or their hire to do it.

Generally the foundry will support multiple CAD access
although they will always have a preference.

I suggest looking at some ASIC design houses' collateral
that speaks to their design flow (which they "sell" that story
to their customers, to get the job). I think your summary is
roughly right but I don't do RTL design or synthesis in my
kind of products. Scrub a few legit ASIC shops together
and you should arrive at a pretty good idea of the mainstream.

 

[ThisIsNotSam]

Your story has an issue in that you have design steps and verification steps as a sequence of events, whereas in reality the verification flow runs in parallel to design. It also does not fully describe the feedback loops, which there are many.

A common set of design steps is: specification -> high-level model or C code -> RTL -> logic synthesis ->physical synthesis -> sign-off. Physical synthesis can be broken down into multiple steps, including power plan, floorplan, partitioning, placement, CTS, route, opt, fill, stream out.

 

[Noor ul ain]

Designing digital Application-Specific Integrated Circuits (ASICs) from scratch involves these steps:

1. **Requirements Gathering**: The first step is to understand what the ASIC is supposed to do. This involves gathering requirements from stakeholders and defining the functionality of the ASIC.

2. **System Design**: Once the requirements are clear, the next step is to design the system. This involves creating a high-level design of the ASIC, including its architecture and data flow.

3. **Logic Design**: The system design is then converted into a logic design. This involves creating a detailed design of the ASIC using logic gates and flip-flops.

4. **RTL Coding**: The logic design is then converted into Register Transfer Level (RTL) code. This code describes the exact behavior of the ASIC.

5. **Functional Verification**: The RTL code is then tested to ensure it behaves as expected. This involves creating test benches and running simulations.

6. **Synthesis**: Once the RTL code is verified, it is synthesized into a gate-level netlist. This netlist describes the physical layout of the ASIC.

7. **Place and Route**: The netlist is then placed and routed. This involves placing the gates on the silicon and routing the wires between them.

8. **Physical Verification**: The physical design is then verified. This involves checking for design rule violations and performing timing analysis.

9. **Fabrication**: Once the design is verified, it is sent to a foundry for fabrication. This involves creating the physical ASIC from the design.

10. **Packaging and Testing**: After fabrication, the ASIC is packaged and tested. This involves placing the ASIC in a package and testing it to ensure it works as expected.