The simplest way for doing indexing in Verilog

[steven852]

Hi,

I have an indexing question in Verilog. For instance, a set of parameters are defined as

paramter [7:0] COMM0 = 8'h00,
COMM1 = 8'h01,
COMM2 = 8'h02,
COMM3 = 8'h03,
COMM4 = 8'h05,
COMM5 = 8'h07;

can I later on use COMM[ADDR}? ADDR is a 3-bit input. I guess I can't. If not, what is the simplest way to make such indexing?

Thanks

 

[quan228228]

Re: Indexing in Verilog

I think you can use "case" statement.

for example:

case (ADDR)
3'b000: COMM = ...;
3'b001: COMM = ...;
...............
default:
COMM = ...;
endcase


I hope this can clear your doubt.

David

 

[echo47]

Re: Indexing in Verilog

Correct, you can't write COMM[ADDR] that way.

Maybe pass a 64-bit parameter and access it like this (it outputs the eight bytes in sequence):

module top (clk, outbyte);
  parameter   [63:0] COMM = 64'h17_13_07_05_03_02_01_00;
  input              clk;
  reg          [2:0] ADDR = 0;
  output reg   [7:0] outbyte;

  always @ (posedge clk) begin
    outbyte <= COMM >> (ADDR * 8);
    ADDR <= ADDR + 1;
  end
endmodule

Still ugly though.

 

[nand_gates]

Re: Indexing in Verilog

here is same thing in a little different way!

module test();
   integer i;
   
   parameter npar = 7;
   parameter wpar = 8;
   parameter [npar*wpar -1:0] COMM_array = {8'h00, 8'h01, 8'h02, 8'h03, 8'h05, 8'h07, 8'h08}; 
   function [wpar -1 : 0]COMM;
      input [2:0] index;
      begin
         COMM = COMM_array >> (npar - index -1)*wpar;
      end
   endfunction

   initial begin
      for(i=0; i<7; i=i+1) begin
         $display("COMM[%0d] = %h",i, COMM(i));
      end
   end      
endmodule // test