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Hi,
Verilog generate (and so is VHDL generate) is an elab time loop unrolling and not run time one. It is inline with what's required for Hardware modeling, in hardware you can't have dynamic number of adders for example. Having said that some tools combine elab-and-simulation under one commonad, for instance Modelsim. I believe VCSMX also has that capability.
If you want to use same instance in mutltiple times in same way then people use generate .
Regarding unrolling of the logic some simulators will give flexibility to take generics/parameter at simulation time ( Modelsim) where you are unrolling it in simulation time but there also still it is at elobaration stage only . Bcos modelsim first it will compile then elobrate the design during simulation .
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