What to do if post layout timing not matching to synthesis

[steven852]

I wonder what to do if the post layout timing analysis not matching to the synthesis results. The synthesis results met all the timings but the post layout timing doesn't meet. Besides solving all conjestion problems, there seems no valid means on the layout side. What else can I do?

Thanks

 

[Nandy]

Re: What to do if post layout timing not matching to synthes

If there is not too many violated paths, you can fix one by one. If too many to fix, the clock speed has to be decreased.
Check this link out for timing ECO.
https://www.nandigits.com/timing_eco.htm
You can also ask back-end to move some gates, if some gates position is not optimized.
https://www.nandigits.com/view_cells_in_layout.htm

 

[semi_jl]

Refloorplan, even resynthesis.

 

[patrickli]

Re: What to do if post layout timing not matching to synthes

Pre-route and post-route will check differently. synthsis meet doesn't mean meet in post-route. some path only be checked in Post-route, unless you modify some default option when synthsis. ideal clock and CTS are also differently.

 

[stevepre]

Re: What to do if post layout timing not matching to synthes

It's pretty common to have synthesis pass while failing on post layout timing.

Re-synthesis with higher margin, work with backend team by giving them more information on the floorplan, ....

 

[wangkl]

re-route manually,
re-synthesis with enough margin,
replace some hi-Vt cell with low-Vt cells
remove some secondary-level power-gating logic
adjust floorplan, change congestion target
change area target.
even considering re-coding the rtl ...

 

[au_sun]

Re: What to do if post layout timing not matching to synthes

As stevepre said, it is common to get timing violation in the Post layout stage,


is that violation value is too big to fix at the Layout stage,

If so u can fix it and closure the timing,

Other wise u have to go back to placement stage or synthesis stage to fix those violation and then redo the layout again for better timing

 

[steven852]

Re: What to do if post layout timing not matching to synthes

I agree with what stevepre and au_sun said and this is what we've practised. But one thing I am not sure: after many tries, how to tell that the P&R tool cannot make it so that refloorplanning, resynthesis or re-coding is needed. I guess I lack experience to make judgement here but only to try more possibilities.

 

[funster]

Re: What to do if post layout timing not matching to synthes

for setup time violation, your can refloorplan or resynthesis or skew

clock edge intentionally to generate some useful skew to extend

clock cycle in timing critical path. for hold time violation, you can add

delay cell in problem path to eliminate the problem.

best regards

I wonder what to do if the post layout timing analysis not matching to the synthesis results. The synthesis results met all the timings but the post layout timing doesn't meet. Besides solving all conjestion problems, there seems no valid means on the layout side. What else can I do?

Thanks