shaharkl
Newbie
Hi,
Among the most common async clocks data interface designs is the gray pointer FIFO designs.
Commonly the FIFO is an array of sequential cells at the transmit side.
Also common is to implement this array using edge triggered DFF (unless your design is latch based...).
Why not use level sensitive latch cells to implement this array ?
I am looking for answers both from static-timing-analysis point of view and also from CDC design perspective .
Thanks
SK
Among the most common async clocks data interface designs is the gray pointer FIFO designs.
Commonly the FIFO is an array of sequential cells at the transmit side.
Also common is to implement this array using edge triggered DFF (unless your design is latch based...).
Why not use level sensitive latch cells to implement this array ?
I am looking for answers both from static-timing-analysis point of view and also from CDC design perspective .
Thanks
SK