Crosstalk on common clock path

[chevuturi]

Hello, How to calculate setup and hold on common clock path if we have crosstalk delay ? And I did not understand The below statement : is it because the hold is calculated at zeroth cycle ?
There is one important difference between hold and setup analyses related to crosstalk on common portion of clock path (launch and capture). Launch and capture clock edge are normally the same edge for hold analysis. Clock edge through common clock portion cannot have different crosstalk contributions for launch clock path and capture clock path. Therefore, the worst-case hold analysis removes crosstalk contribution from common clock path.
Setup analysis concerns two different edges of clock which may be impacted differently in time. Thus, common path crosstalk contributions are considered for both launch and capture paths during setup analysis.

 

[ThisIsNotSam]

we can say crosstalk adds jitter. this delay depends on the activity of the circuit. so, from one cycle to the next, you may have more or less crosstalk, which would create differences in arrival time between edge at t=0 and edge at t=1

 

[chevuturi]

Thanks Professor , I am good now

 

[D.A.(Tony)Stewart]

Crosstalk may be especially significant for sub-harmonic synchronous noise and unbuffered FF's that toggle the state from an external event backdriving the output. Yet normally sub-harmonic crosstalk occurs synchronously after the active clock edge from counters not during the clock edge unless there is an extreme threshold skew. (uncommon)

All registers for external use must be buffered for this reason.

This is also why critical signals are differential balanced with guarding.