Junior Member level 3
I know that set_clock_uncertainty is for taking the clock skew and jitter into account during pre-layout timing analysis. But, after post P&R we have a propagated clock where the skew is known. My question is that if I put the set_clock_uncertainty contraint in sdc for post P&R STA, does it increase the pessemism in hold analysis? In my opinion, we can set set_clock_uncertainty only for considering the jitter in post layout and to increase the pessemism we can use the set_timing_derate. However, the jitter does not affect the hold, so the use of set_clock_uncertainty is meaningless in post layout hold analysis. Is that right?