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Recent content by malikkhaled

  1. M

    FSM Based Controller

    Thanks for your help, but i want this design to start processing when input start is 1 and finish the task and output is available when done flag is 1. Here, in your modified design i have to make start on and off to complete the task which is not desired in my case. Just look at the module as a...
  2. M

    FSM Based Controller

    Hi, I need to implement radix-4 booth encoded modular multiplier for 256-bits. My design is working fine without a controller part, but to automatize it, which is required when used in integration with some other modules in the design of a processor. i write a small FSM based controller possess...
  3. M

    Large (256x256) Multiplier in verilog

    I am using Xilinx virtex-6 family. Yes you are right i manually instantiated DSPs blocks in my 64-bit multiplier and it works well, the confusion arises in 128-bit multiplication using karatsuba technique. Dx and Dy can be negative so do i need a signed multiplier to multiply (DxDy)? In my...
  4. M

    Large (256x256) Multiplier in verilog

    I am designing (256x256)-bit Multiplier using DSP blocks available on Xilinx FPGAs. I split operands into several chunks of 64-bits, using Karatsuba technique 256-bit multiplier can be constructed using 3, 128-bit multipliers each of which are further realized by 3, 64-bit multipliers. i have...
  5. M

    Verilog Code for LED blinking

    Hi everyone, I have an assignment to do i.e, 8 LEDs blinking one after the other on Spartan 3E board. The pattern for LEDs should be started from right most LED and continue to the left one. after one round completion it should again be started from right. I know the basics to divide clock, the...
  6. M

    double and algorithm in Verilog

    multiplier algorithm in Verilog i want to implement double ,add and reduce algorithm for modular multiplication, but unfortunately i am not able to get correct result. my algorithms works as: the register s1, s2 hold iterative results which are being initialized by 0 and operand a, these...
  7. M

    In built DSPs block on FPGA

    Hi, i would like to use in built DSP and multiplier blocks to make add/sub operation faster. anyone would help me with some tutorial or some piece of code for start up. thanks
  8. M

    number of bonded IOBs

    anyone can explain me what is mean by number of bonded IOBs in FPGA, In my design i am using more than the available. what could be the drawback of it? please comments.
  9. M

    need help in verilog

    In my design i have a lot of constants, i want to save these constant in a file and use this file where ever i need it in different modules, but i am getting errors by doing so. anyone could help me here i just post my code. file name: inc.v `default_nettype none `define k 8 `define k1 32...
  10. M

    how to write a loop controller

    i need to implement a loop controller for my project e.g, loop range is 256-0, i know i need to do it by 8-bit counter. i am confused how to do it and instantiate a module inside a counter and make it run for 256 times. any piece of code with some explanation would be helpful
  11. M

    montgomery multiplication

    what i am trying to do is, i have the adder module (add_sub) that adds two 256 bits number and the output is v1. The second module performs multiplication (2U), where u is either s1 and s2 based on b(i). All this is done for a single bit of b(multiplier) in one clock cycle. In same cycle s1 and...
  12. M

    montgomery multiplication

    here i post my code for multiplying two 256 bit numbers mod P(254 bit number). i instantiate two module one is "amulb" and other is "add_sub". s1 and s2 are signals that holds the intermediate result and and v1 and v2 are two variables. This module will perform multiplication in 256 clock...
  13. M

    how to handle large numbers in VHDL

    yes i am using unsigned types from ieee.numeric_std library. in test bench i used a conversion function to convert decimal into binary like "a<= conv_std_logic_vector (1157777,256)", i think the problem could be here i need your suggestion.
  14. M

    how to handle large numbers in VHDL

    hi, i am doing encryption and decryption and my algorithm inputs sizes is 256 bits. in test bench i am getting an error like "555677895559 exceeds maximum integer value ", although i didn't declare it as an integer. constant P: std_logic_vector(255 downto...
  15. M

    addition mod m in verilog

    i want to do x+y mod m,,using this algorithm x1= x+y; x2= x1-m; if x2>=0 then out = x2; else out =x1; here is the code... ////////////////////////////////////// module adder_subtractor ( input [7:0]x, input [7:0]y,output [7:0] out); parameter m=256; wire [8:0] x1,x2,c; assign x1[8:0]=...
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