FSM Based Controller

[malikkhaled]

Hi,
I need to implement radix-4 booth encoded modular multiplier for 256-bits. My design is working fine without a controller part, but to automatize it, which is required when used in integration with some other modules in the design of a processor. i write a small FSM based controller possess only two states (Zero and one). The state Zero is triggered when the input signal start is set to 1, an initial state. In this state zero internal signal load is set to 1 that is condition for loading internal registers with their initial values. In state one, the normal flow is executed and it stays in state one for 129 clock cycles which is achieved through 8-bit counter. after 129 clock cycles result is available and the done signal is triggered to 1.
Here i am going to post my code the only problem is with FSM, i am not an expert so kindly help me to make this code in working order.

[syntax=verilog]
`define k 256
`define p 134161
`define k2 259
module boothmultiplier( input [`k-1:0] a,
							   input [`k-1:0] b,
							   input clk,
							   input start,
	             				 	   output reg[`k-1:0] out
    );

reg [`k-1:0] t;
reg [`k2-1:0] b2;
wire [`k-1:0]t1,t2,s1;
wire [2:0] bi;
wire equal_zero, done,cadd;
reg [7:0] count;
reg state,load;
parameter zero= 1'b0, one=1'b1; 
///////////////////////////////////
assign bi=b2[`k2-1:`k2-3];
//assign s1= bi?a:0;
assign equal_zero= count?1'b0:1'b1;
assign done= equal_zero?1'b1:1'b0;
///left shift 4 mod p ////
left_shift_4_r8 lh(t,t1);
/// booth encoder /////
booth_encoder be(a,bi,t2,cadd);
//// add/subtractor////
add_sub_modp ba(t1,t2, cadd, s1);
always @ (posedge clk)
begin
if (load)
t<=0; 
else if (~equal_zero) begin
t<=s1;
end
end
//////////////// left shift of input b//////////////////////
always @(posedge clk)
begin
if (load) begin
b2<={2'b00,b,1'b0}; 
count<= 8'd129; 
end
else if (~equal_zero)
begin
b2<= {b2[`k2-3:0],2'b0};////k-3
count<= count-1;
end
else if (~count)
out<=t;
end
//////////////////////////////////////////////////////////////////

////////// controller////////////
always @ (posedge clk)
begin
if (start)
state<= zero;
case (state)
begin
zero: if (~equal_zero)
state<= one;
one: if (done)
state<= zero;
end
end case
end

always @ (state)
begin
if (state==zero)
load = 1'b1;
else if (state==one)
load=1'b0;
end
endmodule 
[/syntax]

 

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---

Code Verilog - [expand]
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////////// controller////////////
always @ (posedge clk) begin
  if (start)
    state<= zero; // this will behave as a reset, you shouldn't have it as a separate if with no else clause
  else
    case (state)  // case doesn't have a begin... and ends with endcase not end case
      zero: if (~equal_zero) state<= one;
              else                 state <= zero; // you should always explicitly define both transitions
      one: if (done) state<= zero;
             else       state <= one; // same thing here, define both transitions
    endcase
  end
end

---

Not sure how the original even compiled.

Regards

 

[malikkhaled]

Thanks for your help, but i want this design to start processing when input start is 1 and finish the task and output is available when done flag is 1. Here, in your modified design i have to make start on and off to complete the task which is not desired in my case. Just look at the module as a black box having starts and other input ports and done and output ports. Every time when start input is set to 1 and it outputs the result after 129 clock cycles and which is indicated by the done signal.
How to change this to accommodate only the start=1, more precisely how to avoid else condition in controller part.

 

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Get rid of the if and put the start inside the case statement, better yet add a if (reset) state <= initial_state_value;... and a default clause in the case.

From your question it appears you don't have much of a grasp on designing an FSM. Perhaps you should do a search on designing an FSM. In order to write an HDL you need to understand the hardware you are trying to build.

Regards