#### malikkhaled

##### Junior Member level 1

I need to implement radix-4 booth encoded modular multiplier for 256-bits. My design is working fine without a controller part, but to automatize it, which is required when used in integration with some other modules in the design of a processor. i write a small FSM based controller possess only two states (Zero and one). The state Zero is triggered when the input signal start is set to 1, an initial state. In this state zero internal signal load is set to 1 that is condition for loading internal registers with their initial values. In state one, the normal flow is executed and it stays in state one for 129 clock cycles which is achieved through 8-bit counter. after 129 clock cycles result is available and the done signal is triggered to 1.

Here i am going to post my code the only problem is with FSM, i am not an expert so kindly help me to make this code in working order.

Code:

```
[syntax=verilog]
`define k 256
`define p 134161
`define k2 259
module boothmultiplier( input [`k-1:0] a,
input [`k-1:0] b,
input clk,
input start,
output reg[`k-1:0] out
);
reg [`k-1:0] t;
reg [`k2-1:0] b2;
wire [`k-1:0]t1,t2,s1;
wire [2:0] bi;
wire equal_zero, done,cadd;
reg [7:0] count;
reg state,load;
parameter zero= 1'b0, one=1'b1;
///////////////////////////////////
assign bi=b2[`k2-1:`k2-3];
//assign s1= bi?a:0;
assign equal_zero= count?1'b0:1'b1;
assign done= equal_zero?1'b1:1'b0;
///left shift 4 mod p ////
left_shift_4_r8 lh(t,t1);
/// booth encoder /////
booth_encoder be(a,bi,t2,cadd);
//// add/subtractor////
add_sub_modp ba(t1,t2, cadd, s1);
always @ (posedge clk)
begin
if (load)
t<=0;
else if (~equal_zero) begin
t<=s1;
end
end
//////////////// left shift of input b//////////////////////
always @(posedge clk)
begin
if (load) begin
b2<={2'b00,b,1'b0};
count<= 8'd129;
end
else if (~equal_zero)
begin
b2<= {b2[`k2-3:0],2'b0};////k-3
count<= count-1;
end
else if (~count)
out<=t;
end
//////////////////////////////////////////////////////////////////
////////// controller////////////
always @ (posedge clk)
begin
if (start)
state<= zero;
case (state)
begin
zero: if (~equal_zero)
state<= one;
one: if (done)
state<= zero;
end
end case
end
always @ (state)
begin
if (state==zero)
load = 1'b1;
else if (state==one)
load=1'b0;
end
endmodule
[/syntax]
```