double and algorithm in Verilog

[malikkhaled]

multiplier algorithm in Verilog

i want to implement double ,add and reduce algorithm for modular multiplication, but unfortunately i am not able to get correct result. my algorithms works as: the register s1, s2 hold iterative results which are being initialized by 0 and operand a, these registers are updated in each iteration by values of t1 and t2 registers depending on bit of operand b, finally s1 register holds the final result(ab mod p). here i am posting my code, any help would be appreciated.

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Code Verilog - [expand]
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module multiplier(
    input [7:0] a,
    input [7:0] b,
    input clk,
    input reset,
    output reg[7:0] out
    );
reg [7:0] s1,s2,b2;
wire [7:0]t1,t2,u;
wire bi;
reg [2:0] count;
assign bi=b2[7];
assign u= bi? s2:s1;
///////// calculate t1= 2u mod p(31)///////
left_shift shift1(u,t1);
//////// calculate t2= s1+s2 mod p/////
adder_dub add1(s1,s2,1'b0,t2);
 
always @ (posedge clk)
 
if (~reset)
begin
s1=0; s2= a;
count= 3'd7;
 
end
/////////////////////////////////////////////////////////////////////////////
else begin 
if (count >= 0) begin
 
if (bi==1)
begin
s1=t1;
s2=t2;
end
else begin
s1=t2;
s2=t1;
end
count= count-1;
end
out<= s1;
end
//////////////// left shift of input b//////////////////////
always @(posedge clk)
if (~reset) begin
b2=b;
end
else begin
b2= {b2[6:0],1'b0};
end
endmodule

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