montgomery multiplication

[malikkhaled]

here i post my code for multiplying two 256 bit numbers mod P(254 bit number). i instantiate two module one is "amulb" and other is "add_sub". s1 and s2 are signals that holds the intermediate result and and v1 and v2 are two variables. This module will perform multiplication in 256 clock cycles. but i am getting errors in generate command, anyone here could help me.

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Code VHDL - [expand]
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[syntax=asp]p1:process (clk)
variable v1,v2: std_logic_vector(k3 downto 0);
begin
if reset='1' then
s1 <=(others=> '0');
s2<= a;
else 
if clk'event and clk='1' then
gen2:for i in k3 to 0 generate
--begin
---------- mux---------------
u<= s2 when b(i)='1' else s1;
------------ instantiation-------
uu1:amulb port map (u,'1',v1);
uu2:add_sub port map(s1,s2,cin,v2,c1);
------------ mux----------------
s1<= v1 when b(i)='1' else v2;
s2<= v2 when b(i)='1' else v1;
end generate;
end if;
end process;
end Behavioral;

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[ads_ee]

Since you didn't post any of the definitions of the signals I'll just assume they are all std_logic_vectors.

Are you trying to write a software loop? You can't assign u in multiple passes through the loop using b(i) same goes for all the reset of the code you have in the generate.

Think about what you've written...

Your telling the compiler to create K3+1 copies of everything in the generate loop. So you have k3+1 copies of amulb that have all their inputs and outputs shorted to the same u and v1 same goes for add_sub.

You need to know what hardware you want and then write HDL that represents the hardware.

 

[malikkhaled]

Since you didn't post any of the definitions of the signals I'll just assume they are all std_logic_vectors.

Are you trying to write a software loop? You can't assign u in multiple passes through the loop using b(i) same goes for all the reset of the code you have in the generate.

Think about what you've written...

Your telling the compiler to create K3+1 copies of everything in the generate loop. So you have k3+1 copies of amulb that have all their inputs and outputs shorted to the same u and v1 same goes for add_sub.

You need to know what hardware you want and then write HDL that represents the hardware.

what i am trying to do is, i have the adder module (add_sub) that adds two 256 bits number and the output is v1. The second module performs multiplication (2U), where u is either s1 and s2 based on b(i). All this is done for a single bit of b(multiplier) in one clock cycle. In same cycle s1 and s2 are computed base on v1 and v2. so for a next cycle now u will get values of s1 and s2 with respect of b(i-1); all of my signals are std_logic_vector;

 

[ads_ee]

You're describing a sequential process over each bit of the multiplicand.
But that isn't what you wrote with that generate block. The generate block gets unrolled into parallel hardware. Think in terms of what does the code look like if you substituted every possible i in the generate and wrote all that code produced in place of the generate block.